Datasheet

High Performance 16-bit CPU with 4-Stage Pipeline
80 ns Instruction Cycle Time at 25 MHz CPU Clock
400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)
Enhanced Boolean Bit Manipulation Facilities
Additional Instructions to Support HLL and Operating Systems
Register-Based Design with Multiple Variable Register Banks
Single-Cycle Context Switching Support
16 MBytes Total Linear Address Space for Code and Data
1024 Bytes On-Chip Special Function Register Area
16-Priority-Level Interrupt System with 27 Sources, Sample-Rate down to 40 ns
8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
Clk. Generation via on-chip PLL (1:1.5/2/2.5/3/4/5), via prescaler or via direct clk. inp.
On-Chip Memory Modules
1 KByte On-Chip Internal RAM (IRAM)
2 KBytes On-Chip Extension RAM (XRAM)
On-Chip Peripheral Modules
4-Channel 10-bit A/D Converter with Programm. Conversion Time down to 7.8 µs
Two Multi-Functional General Purpose Timer Units with 5 Timers
Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
–I
2
C Bus Interface (10-bit Addressing, 400 KHz) with 2 Channels (multiplexed)
Up to 8 MBytes External Address Space for Code and Data
Programmable External Bus Characteristics for Different Address Ranges
Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
Five Programmable Chip-Select Signals
Idle and Power Down Modes with Flexible Power Management
Programmable Watchdog Timer and Oscillator Watchdog
On-Chip Real Time Clock
Up to 76 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
On-Chip Bootstrap Loader
100-Pin MQFP / TQFP Package
Data Sheet 1 1999-07
C166 Family of C161PI
High-Performance CMOS 16-Bit Microcontrollers
Preliminary
C161PI 16-Bit Microcontroller