Datasheet

C161K
C161O
Data Sheet 37 V2.0, 2001-01
Prescaler Operation
When prescaler operation is configured (CLKCFG = 1XX
B
) the CPU clock is derived
from the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of
f
CPU
is half the frequency of f
OSC
and the high and low time of f
CPU
(i.e.
the duration of an individual TCL) is defined by the period of the input clock
f
OSC
.
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of
f
OSC
for any TCL.
Direct Drive
When direct drive is configured (CLKCFG = 0XX
B
) the CPU clock is directly driven from
the internal oscillator with the input clock signal.
The frequency of
f
CPU
directly follows the frequency of f
OSC
so the high and low time of
f
CPU
(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock
f
OSC
.
The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:
TCL
min
= 1/f
OSC
× DC
min
(DC = duty cycle)
For two consecutive TCLs the deviation caused by the duty cycle of
f
OSC
is compensated
so the duration of 2TCL is always 1/
f
OSC
. The minimum value TCL
min
therefore has to
be used only once for timings that require an odd number of TCLs (1, 3, …). Timings that
require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/
f
OSC
.
Table 9 C161K/O Clock Generation Modes
CLKCFG
(P0H.7-5)
CPU Frequency
f
CPU
= f
OSC
× F
External Clock
Input Range
Notes
0XX
f
OSC
× 1 1 to 25 MHz Direct drive
1)
1XX f
OSC
/ 2 2 to 50 MHz CPU clock via prescaler
1)
The maximum frequency depends on the duty cycle of the external clock signal.