Datasheet

C161K
C161O
Data Sheet 27 V2.0, 2001-01
SSCEIC b FF76
H
BB
H
SSC Error Interrupt Control Register 0000
H
SSCRB F0B2
H
E 59
H
SSC Receive Buffer XXXX
H
SSCRIC b FF74
H
BA
H
SSC Receive Interrupt Control Register 0000
H
SSCTB F0B0
H
E 58
H
SSC Transmit Buffer 0000
H
SSCTIC b FF72
H
B9
H
SSC Transmit Interrupt Control Register 0000
H
STKOV FE14
H
0A
H
CPU Stack Overflow Pointer Register FA00
H
STKUN FE16
H
0B
H
CPU Stack Underflow Pointer Register FC00
H
SYSCON b FF12
H
89
H
CPU System Configuration Register
1)
0XX0
H
T2 FE40
H
20
H
GPT1 Timer 2 Register 0000
H
T2CON b FF40
H
A0
H
GPT1 Timer 2 Control Register 0000
H
T2IC b FF60
H
B0
H
GPT1 Timer 2 Interrupt Control Register 0000
H
T3 FE42
H
21
H
GPT1 Timer 3 Register 0000
H
T3CON b FF42
H
A1
H
GPT1 Timer 3 Control Register 0000
H
T3IC b FF62
H
B1
H
GPT1 Timer 3 Interrupt Control Register 0000
H
T4 FE44
H
22
H
GPT1 Timer 4 Register 0000
H
T4CON b FF44
H
A2
H
GPT1 Timer 4 Control Register 0000
H
T4IC b FF64
H
B2
H
GPT1 Timer 4 Interrupt Control Register 0000
H
T5 FE46
H
23
H
GPT2 Timer 5 Register 0000
H
T5CON b FF46
H
A3
H
GPT2 Timer 5 Control Register 0000
H
T5IC b FF66
H
B3
H
GPT2 Timer 5 Interrupt Control Register 0000
H
T6 FE48
H
24
H
GPT2 Timer 6 Register 0000
H
T6CON b FF48
H
A4
H
GPT2 Timer 6 Control Register 0000
H
T6IC b FF68
H
B4
H
GPT2 Timer 6 Interrupt Control Register 0000
H
TFR b FFAC
H
D6
H
Trap Flag Register 0000
H
WDT FEAE
H
57
H
Watchdog Timer Register (read only) 0000
H
WDTCON b FFAE
H
D7
H
Watchdog Timer Control Register
2)
00XX
H
ZEROS b FF1C
H
8E
H
Constant Value 0’s Register (read only) 0000
H
1)
The system configuration is selected during reset.
2)
The reset value depends on the indicated reset source.
Table 6 C161K/O Registers, Ordered by Name (cont’d)
Name Physical
Address
8-Bit
Addr.
Description Reset
Value