Datasheet

C161K
C161O
Data Sheet 7 V2.0, 2001-01
RSTIN 65 I/O Reset Input with Schmitt-Trigger characteristics. A low level
at this pin while the oscillator is running resets the C161K/O.
An internal pullup resistor permits power-on reset using only
a capacitor connected to
V
SS
. A spike filter suppresses input
pulses < 10 ns. Input pulses >100 ns safely pass the filter.
The minimum duration for a safe recognition should be
100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit BDRSTEN
in register SYSCON) the RSTIN
line is internally pulled low
for the duration of the internal reset sequence upon any reset
(HW, SW, WDT). See note below this table.
Note: To let the reset configuration of PORT0 settle a reset
duration of ca. 1 ms is recommended.
RST
OUT
66 O Internal Reset Indication Output. This pin is set to a low level
when the part is executing either a hardware-, a software- or
a watchdog timer reset. RSTOUT
remains low until the EINIT
(end of initialization) instruction is executed.
NMI 67 I Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C161K/O to go into
power down mode. If NMI
is high, when PWRDN is
executed, the part will continue to run in normal mode.
If not used, pin NMI
should be pulled high externally.
P6
P6.0
P6.1
P6.2
P6.3
68
69
IO
O
O
Port 6 is a 4-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 6 outputs can be configured as push/
pull or open drain drivers.
The Port 6 pins also serve for alternate functions:
CS0
Chip Select 0 Output
CS1
Chip Select 1 Output
70
71
O
O
CS2 Chip Select 2 Output
CS3
Chip Select 3 Output
These chip select outputs are only available in the C161O.
Table 2 Pin Definitions and Functions (cont’d)
Symbol Pin
Num
Input
Outp.
Function