Datasheet

Datasheet 11 Revision 2.3, 2013-05-16
ISOFACE™
ISO1H816G
Functional Description
more ICs is needed. All ICs share the same clock and
chip select port of the SPI master. That is all ICs are
active and addressed simultaneously. The data out of
the µC is connected to the SI of the first IC in the line.
Each SO of an IC is connected to the SI of the next IC
in the line.
Figure 10 SPI bus all ICs in a “daisy chain”
configuration
The µC feeds to data bits into the SI of IC1 (first IC in
the chain). The bits coming from the SO of IC1 are
directly shifted into the SI of the next IC. As long as the
chip select is inactive (logic high) all the IC SPIs ignore
the clock (SCLK) and input signals (SI) and all outputs
(SO) are in tristate. As long as the chip select is active
the SPI register works as a simple shift register. With
each clock signal one input is shifted into the SPI
register (SI), each bit in the shift register moves one
position further within the register, and the last bit in the
SPI shift register is shifted out of SO. This continous as
long as the chip select is active (logic low) and clock
signals are applied. The data is then only taken over to
the output buffers of each IC when the CS signal
changes to high from low and recognized as valid data
by the internal modulo counter.
3.6 Transmission Failure Detection
There is a failure detection unit integrated to ensure
also a stable functionality during the integrated
coreless transformer transmission. This unit decides
wether the transmitted data is valid or not. If four times
serial data coming from the internal registers is not
accepted the output stages are switched off until the
next valid data is received.
SPI - Interface
Output lines
SPI - Interface
Output lines
µC
SPI 1
CLK
Tx a1
Tx a2
Number of adressed ICs = n
Number of necessary control and data ports = 3
All ICs are adressed by the common chip select
ICn
IC1
SCLK
CS
SI
SCLK
CS
SO
SI