Datasheet

ISOFACE™
ISO1H815G
Functional Description
Datasheet 8 Revision 2.3, 2013-05-16
3 Functional Description
3.1 Introduction
The ISOFACE ISO1H815G includes 8 high-side power
switches that are controlled by means of the integrated
parallel interface. The interface is 8bit µC compatible.
Furthermore a direct control mode can be selected that
allows the direct control of the outputs OUT0...OUT7 by
means of the inputs D0...D7 without any additional logic
signal. The IC can replace 8 optocouplers and the 8
high-side switches in conventional I/O-Applications as
a galvanic isolation is implemented by means of the
integrated coreless transformer technology. The µC
compatible interfaces allow a direct connection to the
ports of a microcontroller without the need for other
components. Each of the 8 high-side power switches is
protected against short to Vbb, overload,
overtemperature and against overvoltage by an active
zener clamp.
The diagnostic logic on the power chip recognizes the
overtemperature information of each power transistor
The information is send via the internal coreless
transformer to the pin DIAG
at the input interface.
3.2 Power Supply
The IC contains 2 galvanic isolated voltage domains
that are independent from each other. The input
interface is supplied at VCC and the output stage is
supplied at Vbb. The different voltage domains can be
switched on at different time. The output stage is only
enabled once the input stage enters a stable state.
3.3 Output Stage
Each channel contains a high-side vertical power FET
that is protected by embedded protection functions.
The continuous current for each channel is 1.2A (all
channels ON).
3.3.1 Output Stage Control
Each output is independently controlled by an output
latch and a common reset line via the pin DIS
that
disables all eight outputs and reset the latches. The
parallel input data is transferred to the input latches
with a high-to-low transition of the signal WR
(write)
while the CS
is logic low. A low-to-high transition of CS
transfers then the data of the input latches to the output
buffer.
3.3.2 Power Transistor Overvoltage
Protection
Each of the eight output stages has it own zener clamp
that causes a voltage limitation at the power transistor
when solenoid loads are switched off. V
ON
is then
clamped to 47V (min.).
Figure 3 Inductive and overvoltage output
clamp (each channel)
Energy is stored in the load inductance during an
inductive load switch-off.
Figure 4 Inductive load switch-off energy
dissipation (each channel)
While demagnetizing the load inductance, the energy
dissipation in the DMOS is
with an approximate solution for R
L
> 0Ω:
Vz
Vbb
GNDbb
OUTx
V
ON
Vbb
E
L
12⁄ LI
L
2
××=
E
LGNDbbV
bb
OUT x
E
R
L
R
L
E
Load
Z
L
Vbb
E
bb
E
AS
Dx
E
AS
E
bb
E
L
E
R
– V
ON CL()
i
L
t()dt×=+=
E
AS
I
L
L×
2R
L
×
----------------
V
bb
V
ON CL()
+()1
I
L
R
L
×
V
ON CL()
-------------------------+
⎝⎠
⎛⎞
ln××=