Datasheet

IRFP4310ZPbF
www.irf.com 7
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
V
GS
V
DS
90%
10%
t
d(on)
t
d(off)
t
r
t
f
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
t
p
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
V
DS
+
-
V
DD
DRIVER
A
15V
20V
V
GS
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
V
DS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
R
D
V
GS
R
G
D.U.T.
10V
+
-
V
DD
Vds
Vgs
Id
Vgs(th)
Qgs1
Qgs2QgdQgodr
1K
VCC
DUT
0
L
S
20K
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple ≤ 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P. W .
Period
*** V
GS
= 5V for Logic Level Devices
***
+
-
+
+
+
-
-
-



R
G
V
DD
• dv/dt controlled by R
G
• Driver same type as D.U.T.
• I
SD
controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T

**
*
*
Use P-Channel Driver for P-Channel Measurements
** Reverse Polarity for P-Channel
Fig 21. Diode Reverse Recovery Test Circuit for HEXFET
®
Power MOSFETs