Datasheet

CoolSET
®
-F3
ICE3A1065ELJ
Functional Description
Version 2.3 9 19 Nov 2012
connected to the VCC pin. This VCC charge current is
controlled to 0.9mA by the Startup Cell. When the V
VCC
exceeds the on-threshold V
CCon
=18V, the bias circuit
are switched on. Then the Startup Cell is switched off
by the Undervoltage Lockout and therefore no power
losses present due to the connection of the Startup Cell
to the Drain voltage. To avoid uncontrolled ringing at
switch-on a hysteresis start up voltage is implemented.
The switch-off of the controller can only take place after
Active Mode was entered and V
VCC
falls below 10.5V.
The maximum current consumption before the
controller is activated is about 250μA.
When V
VCC
falls below the off-threshold V
CCoff
=10.5V,
the bias circuit switched off and the soft start counter is
reset. Thus it is ensured that at every startup cycle the
soft start starts at zero.
The internal bias circuit is switched off if Latched Off
Mode
or Auto Restart Mode is entered. The current
consumption is then reduced to 250μA.
Once the malfunction condition is removed, this block
will then
turn back on. The recovery from Auto Restart
Mode does not require re-cycling the AC line. In case
Latched Off Mode is entered, VCC needs to be lowered
below 6.23V to reset the Latched Off Mode. This is
done usually by re-cycling the AC line.
When Active Burst Mode is entered, the internal Bias is
switche
d off most of the time but the Voltage Reference
is kept alive in order to reduce the current consumption
below 450μA.
3.3 Improved Current Mode
x3.2
PWM OP
Improved
Current Mode
0.6V
C8
PWM-Latch
CS
FB
R
S
Q
Q
Driver
Soft-Start Comparator
Figure 4 Current Mode
Current Mode means the duty cycle is controlled by the
slo
pe of the primary current. This is done by comparing
the FB signal with the amplified current sense signal.
t
FB
Amplified Current Signal
T
on
t
0.6V
Driver
Figure 5 Pulse Width Modulation
In case the amplified current sense signal exceeds the
FB
signal the on-time T
on
of the driver is finished by
resetting the PWM-Latch (see Figure 5).
The primary current is sensed by the external series
r
esistor R
Sense
inserted in the source of the integrated
CoolMOS
®
. By means of Current Mode regulation, the
secondary output voltage is insensitive to the line
variations. The current waveform slope will change with
the line variation, which controls the duty cycle.
The external R
Sense
allows an individual adjustment of
the maximum source current of the integrated
CoolMOS
®
.
To improve the Current Mode during light load
con
ditions the amplified current ramp of the PWM-OP
is superimposed on a voltage ramp, which is built by
the switch T2, the voltage source V1 and a resistor R1
(see Figure 6). Every time the oscillator shuts down for
maximum duty cycle limitation the switch T2 is closed
by V
OSC
. When the oscillator triggers the Gate Driver,
T2 is opened so that the voltage ramp can start.
In case of light load the amplified current ramp is too
small
to ensure a stable regulation. In that case the
Voltage Ramp is a well defined signal for the
comparison with the FB-signal. The duty cycle is then
controlled by the slope of the Voltage Ramp.
By means of the time delay circuit
which is triggered by
the inverted V
OSC
signal, the Gate Driver is switched-off
until it reaches approximately 156ns delay time (see
Figure 7). It allows the duty cycle to be reduced
continuously till 0% by decreasing V
FB
below that
threshold.