Datasheet

CoolSET
®
-F3
ICE3A1065ELJ
Functional Description
Version 2.3 13 19 Nov 2012
3.5.2 PWM-Latch FF1
The output of the oscillator block provides continuous
pulse to the PWM-Latch which turns on/off the internal
CoolMOS
®
After the PWM-Latch is set, it is reset by the
PWM comparator, the Soft Start comparator or the
Current -Limit comparator. When it is in reset mode, the
output of the driver is shut down immediately.
3.5.3 Gate Driver
VCC
1
PWM-Latch
CoolMOS
®
Gate Driver
Gate
Figure 15 Gate Driver
The driver-stage is optimized to minimize EMI and to
pr
ovide high circuit efficiency. This is done by reducing
the switch on slope when exceeding the internal
CoolMOS
®
threshold. This is achieved by a slope
control of the rising edge at the driver’s output (see
Figure 16).
t
(internal)
V
Gate
5V
ca. t = 130ns
Figure 16 Gate Rising Slope
Thus the leading switch on spike is minimized.
Furt
hermore the driver circuit is designed to eliminate
cross conduction of the output stage.
During power up, when VCC is below the undervoltage
lockout
threshold V
VCCoff
, the output of the Gate Driver
is set to low in order to disable power transfer to the
secondary side.
3.6 Current Limiting
C11
Current Limiting
C10
1.66V
C12
&
0.31V
Leading
Edge
Blanking
220ns
G10
Spike
Blanking
190ns
Propagation-Delay
Compensation
V
csth
Active Burst
Mode
PWM Latch
FF1
10k
D1
1pF
PWM-OP
CS
Latched Off
Mode
Figure 17 Current Limiting Block
There is a cycle by cycle peak c
urrent limiting operation
realized by the Current-Limit comparator C10. The
source current of the integrated CoolMOS
®
is sensed
via an external sense resistor R
Sense
. By means of
R
Sense
the source current is transformed to a sense
voltage V
Sense
which is fed into the pin CS. If the voltage
V
Sense
exceeds the internal threshold voltage V
csth,
the
comparator C10 immediately turns off the gate drive by
resetting the PWM Latch FF1.
A Propagation Delay Compensation is added to
sup
port the immediate shut down of the integrated
CoolMOS
®
with very short propagation delay. Thus the
influence of the AC input voltage on the maximum
output power can be reduced to minimal.
In order to prevent the current limit from distortions
cau
sed by leading edge spikes, a Leading Edge
Blanking is integrated in the current sense path for the
comparators C10, C12 and the PWM-OP.
The output of comparator C12 is activated by the Gate
G
10 if Active Burst Mode is entered. When it is
activated, the current limiting is reduced to 0.31V. This