Datasheet

t
V
SOFTS32
V
SoftS
Gate
Driver
t
t
Soft-Start
CoolSET
®
-F3
ICE3A1065ELJ
Functional Description
Version 2.3 12 19 Nov 2012
Figure 12 Gate drive signal under Soft-Start Phase
Within the soft start period,
the duty cycle is increasing
from zero to maximum gradually (see Figure 12).
In addition to Start-Up, Soft-Start is also activated at
ea
ch restart attempt during Auto Restart.
t
t
V
SoftS
t
V
SOFTS32
4.0V
t
Soft-Start
V
OUT
V
FB
V
OUT
t
Start-Up
Figure 13 Start Up Phase
The Start-Up time t
Start-Up
before the converter output
voltage V
OUT
is settled, must be shorter than the Soft-
Start Phase t
Soft-Start
(see Figure 13).
By means of Soft-Start there is an effective
min
imization of current and voltage stresses on the
integrated CoolMOS
®
, the clamp circuit and the output
overshoot and it helps to prevent saturation of the
transformer during Start-Up.
3.5 PWM Section
Oscillator
Duty Cycle
max
Gate Driver
0.75
Clock
&
G9
1
G8
PWM Section
FF1
R
S
Q
Soft Start
Comparator
PWM
Comparator
Current
Limiting
CoolMOS
®
Gate
Frequency
Jitter
Soft Start
Block
Figure 14 PWM Section Block
3.5.1 Oscillator
The oscillator generates a fixed frequency of 100KHz
wit
h frequency jittering of ±4% (which is ±4KHz) at a
jittering period of 4ms.
A capacitor, a current source and a current sink which
d
etermine the frequency are integrated. The charging
and discharging current of the implemented oscillator
capacitor are internally trimmed, in order to achieve a
very accurate switching frequency. The ratio of
controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of D
max
=0.75.
Once the Soft Start period is over and when the IC goes
i
nto normal operating mode, the switching frequency of
the clock is varied by the control signal from the Soft
Start block. Then the switching frequency is varied in
range of 100KHz ± 4KHz at period of 4ms.