Version 2.3, 19 Nov 2012 C o o l S E T ®- F 3 ICE3A1065ELJ Off-Line SMPS Current Mode Controller with integrated 650V CoolMOS® and Startup Cell (Latched and frequency jitter Mode) Power Management & Supply N e v e r s t o p t h i n k i n g .
CoolSET®-F3 ICE3A1065ELJ Revision History: 2012-11-19 Datasheet Previous Version: V2.2 Page Subjects (major changes since last revision) 25 revised outline dimension for PG-DIP-8 package For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http:// www.infineon.com CoolMOS®, CoolSET® are trademarks of Infineon Technologies AG.
CoolSET®-F3 ICE3A1065ELJ Off-Line SMPS Current Mode Controller with integrated 650V CoolMOS® and Startup Cell (Latched and frequency jitter Mode) Product Highlights • Active Burst Mode to reach the lowest Standby Power Requirements < 100mW • Built-in latched off mode and external latch enable function to increase robustness of the system • Built-in and extendable blanking window for high load jumps to increase system reliability • Built-in soft start • Frequency jitter for low EMI • Robustness to system noi
CoolSET®-F3 ICE3A1065ELJ Table of Contents Page 1 1.1 1.2 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Configuration with PG-DIP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3 3.1 3.2 3.3 3.3.1 3.3.2 3.4 3.5 3.5.1 3.
CoolSET®-F3 ICE3A1065ELJ 6 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 7 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 8 Schematic for recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . .27 Version 2.
CoolSET®-F3 ICE3A1065ELJ Pin Configuration and Functionality 1 Pin Configuration and Functionality 1.1 Pin Configuration with PG-DIP-8 Pin Symbol BL Blanking and Latch 2 FB Feedback 3 CS Current Sense/ 650V1) CoolMOS® Source 4 Drain 650V1) CoolMOS® Drain 5 Drain 650V1) CoolMOS® Drain 6 n.c.
Figure 2 Version 2.3 TLE FB #1 CBK BL 7 3.0V 3.61V 1.35V 4.5V 4.0V 0.1V 1 ms counter 24V VCC T1 T2 3.25kΩ C6b C6a C5 C4 C3 C2 C1 T3 1 G2 G1 & 1 G3 Tj >140°C G5 & & G6 Spike Blanking 8.0us 8us Blanking Time & G11 Active Burst Mode Auto Restart Mode Soft Start Block Latched Off Mode Power-Down Reset Thermal Shutdown Spike Blanking 8.0us 20ms Blanking Time 20ms Blanking Time 0.6V Latched Off Mode Reset VVCC < 6.23V Internal Bias Power Management 18V 5.
CoolSET®-F3 ICE3A1065ELJ Functional Description 3 Functional Description All values which are used in the functional description are typical values. For calculating the worst cases the min/max values which can be found in section 4 Electrical Characteristics have to be considered. 3.1 the BL pin is pulled down to less than 0.1V, the Latch Off Mode is triggered. The Auto Restart Mode reduces the average power conversion to a minimum under unsafe operating conditions.
CoolSET®-F3 ICE3A1065ELJ Functional Description Current Mode means the duty cycle is controlled by the slope of the primary current. This is done by comparing the FB signal with the amplified current sense signal. connected to the VCC pin. This VCC charge current is controlled to 0.9mA by the Startup Cell. When the VVCC exceeds the on-threshold VCCon=18V, the bias circuit are switched on.
CoolSET®-F3 ICE3A1065ELJ Functional Description 3.3.1 Soft-Start Comparator PWM Comparator FB C8 PWM-Latch Oscillator VOSC time delay circuit (156ns) 10kΩ 3.3.2 Gate Driver X3.2 V1 C1 PWM-Comparator The PWM-Comparator compares the sensed current signal of the integrated CoolMOS® with the feedback signal VFB (see Figure 8).
CoolSET®-F3 ICE3A1065ELJ Functional Description 3.4 Startup Phase Soft Start finish Soft Start counter SoftS Soft Start Soft Start V SoftS Soft-Start Comparator C7 & V SoftS2 V SoftS1 Gate Driver G7 Figure 10 Soft Start Phase 0.6V x3.2 5V CS PWM OP R SoftS SoftS Figure 9 Soft Start In the Startup Phase, the IC provides a Soft Start period to control the maximum primary current by means of a duty cycle limitation.
CoolSET®-F3 ICE3A1065ELJ Functional Description The Start-Up time tStart-Up before the converter output voltage VOUT is settled, must be shorter than the SoftStart Phase tSoft-Start (see Figure 13). By means of Soft-Start there is an effective minimization of current and voltage stresses on the integrated CoolMOS®, the clamp circuit and the output overshoot and it helps to prevent saturation of the transformer during Start-Up. VSoftS tSoft-Start VSOFTS32 3.5 PWM Section t Gate Driver 0.
CoolSET®-F3 ICE3A1065ELJ Functional Description is set to low in order to disable power transfer to the secondary side. 3.5.2 PWM-Latch FF1 The output of the oscillator block provides continuous pulse to the PWM-Latch which turns on/off the internal CoolMOS® After the PWM-Latch is set, it is reset by the PWM comparator, the Soft Start comparator or the Current -Limit comparator. When it is in reset mode, the output of the driver is shut down immediately. 3.5.3 3.
CoolSET®-F3 ICE3A1065ELJ Functional Description The overshoot of Signal2 is larger than of Signal1 due to the steeper rising waveform. This change in the slope is depending on the AC input voltage. Propagation Delay Compensation is integrated to reduce the overshoot due to dI/dt of the rising primary current. Thus the propagation delay time between exceeding the current sense threshold Vcsth and the switching off of the integrated internal CoolMOS® is compensated over temperature within a wide range.
CoolSET®-F3 ICE3A1065ELJ Functional Description 3.7 Control Unit the 8.0us spike blanking time, the Auto Restart Mode is activated. For example, if CBK = 0.22uF, IBK = 8.4uA Blanking time = 20ms + CBK x (4.0 - 0.9) / IBK = 100ms The 20ms blanking time circuit after C4 is disabled by the soft stat block such that the controller can start up properly. The Active Burst Mode has basic blanking mode only while the Auto Restart Mode has both the basic and the extendable blanking mode.
CoolSET®-F3 ICE3A1065ELJ Functional Description it starts to count. When the counter reach 20ms and FB signal is still below 1.35V, the system enters the Active Burst Mode. This time window prevents a sudden entering into the Active Burst Mode due to large load jumps. After entering Active Burst Mode, a burst flag is set and the internal bias is switched off in order to reduce the current consumption of the IC to approx. 450uA.
CoolSET®-F3 ICE3A1065ELJ Functional Description 3.7.3 Protection Modes The IC provides several protection features which are separated into two categories. Some enter Latched Off Mode and the others enter Auto Restart Mode. Besides the pre-defined protection feature for the Latch off mode, there is also an external Latch off Enable pin for customer defined Latch off protection features. The Latched Off Mode can only be reset if VCC falls below 6.23V. Both modes prevent the SMPS from destructive states.
CoolSET®-F3 ICE3A1065ELJ Functional Description to charge the capacitor CBK from 0.9V to 4.0V after the switch S1 is released. The charging time from 0.9V to 4.0V are the extendable blanking time. If CBK is 0.22uF and IBK is 8.4uA, the extendable blanking time is around 80ms and the total blanking time is 100ms. In combining the FB and blanking time, there is a blanking window generated which prevents the system to enter Auto Restart Mode due to large load jumps.
CoolSET®-F3 ICE3A1065ELJ Electrical Characteristics 4 Electrical Characteristics Note: All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are not violated. 4.1 Note: Absolute Maximum Ratings Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit.
CoolSET®-F3 ICE3A1065ELJ Electrical Characteristics 4.2 Note: Operating Range Within the operating range the IC operates as described in the functional description. Parameter Symbol min. max. VCC Supply Voltage VVCC VVCCoff 26 V Junction Temperature of Controller TjCon -25 130 °C Junction Temperature of CoolMOS® TjCoolMOS -25 150 °C 4.3 4.3.
CoolSET®-F3 ICE3A1065ELJ Electrical Characteristics 4.3.2 Internal Voltage Reference Parameter Trimmed Reference Voltage 4.3.3 Symbol VREF Limit Values min. typ. max. 4.90 5.00 5.10 Unit Test Condition V measured at pin FB IFB = 0 PWM Section Parameter Symbol Limit Values Unit Test Condition min. typ. max. fOSC1 87 100 113 kHz fOSC2 92 100 108 kHz Tj = 25°C Frequency Jittering Range fjitter - ±4.0 - kHz Tj = 25°C Max. Duty Cycle Dmax 0.70 0.75 0.80 Min.
CoolSET®-F3 ICE3A1065ELJ Electrical Characteristics 4.3.5 Control Unit Parameter Symbol Limit Values min. typ. max. Unit Test Condition VFB = 4V Clamped VBL voltage during Normal Operating Mode VBLclmp 0.85 0.90 0.95 V Blanking time voltage limit for Comparator C3 VBKC3 3.85 4.00 4.15 V Over Load & Open Loop Detection Limit for Comparator C4 VFBC4 4.28 4.50 4.72 V Active Burst Mode Level for Comparator C5 VFBC5 1.23 1.35 1.
CoolSET®-F3 ICE3A1065ELJ Electrical Characteristics 4.3.6 Current Limiting Parameter Symbol Limit Values min. typ. max. Unit Test Condition dVsense / dt = 0.6V/μs (see Figure 20) Peak Current Limitation (incl. Propagation Delay) Vcsth 0.99 1.06 1.09 V Peak Current Limitation during Active Burst Mode VCS2 0.27 0.31 0.37 V Leading Edge Blanking tLEB - 220 - ns CS Input Bias Current ICSbias -1.5 -0.2 - μA Over Current Detection for Latched Off Mode VCS1 1.57 1.66 1.
CoolSET®-F3 ICE3A1065ELJ Temperature derating curve 5 Temperature derating curve Safe Operating Area for ICE3A(B)1065(ELJ) ID = f ( VDS ) parameter : D = 0, TC = 25deg.C 10 ID [A] 1 0.1 tp = tp = tp = tp = tp = DC 0.01 0.1ms 1ms 10ms 100ms 1000ms 0.001 1 10 100 1000 V DS [V] Figure 28 Safe Operating area (SOA) curve (p g p ) SOA temperature derating coefficient [%] 120 100 80 60 40 20 0 0 Figure 29 Version 2.
CoolSET®-F3 ICE3A1065ELJ Outline Dimension 6 Outline Dimension PG-DIP-8 (Plastic Dual In-Line Outline) Figure 30 Version 2.
CoolSET®-F3 ICE3A1065ELJ Marking 7 Marking Marking Figure 31 Version 2.
CoolSET®-F3 ICE3A1065ELJ Schematic for recommended PCB layout 8 Schematic for recommended PCB layout TR1 BR1 FUSE1 L Spark Gap 3 D21 C11 bulk cap X-CAP Vo L1 C1 Spark Gap 1 C12 R11 D11 C21 GND Spark Gap 2 D11 Spark Gap 4 N C2 Y-CAP Y-CAP Z11 C16 CS C4 Y-CAP GND IC11 R12 C3 DRAIN R13 R14 SOFTS F3 CoolSET VCC GND FB NC R21 D13 R23 C22 C23 C14 IC12 F3 CoolSET schematic for recommended PCB layout Figure 32 R22 C15 C13 R24 IC21 R25 Schematic for recommended PCB la
CoolSET®-F3 ICE3A1065ELJ Schematic for recommended PCB layout b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND: These 2 Spark Gaps can be used when the lightning surge requirement is >6KV. 230Vac input voltage application, the gap separation is around 5.5mm 115Vac input voltage application, the gap separation is around 3mm 2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input 3.
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