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BTS 4130QGA 1 Overview 3 2 Block Diagram 5 3 3.1 3.2 3.3 Pin Configuration 6 Pin Assignment 6 Pin Definitions and Functions 6 Voltage and Current Definition 7 4 4.1 4.2 4.3 General Product Characteristics 8 Absolute Maximum Ratings 8 Functional Range 9 Thermal Resistance 9 5 5.1 5.2 5.3 5.3.1 5.4 Power Stage 10 Output ON-State Resistance 10 Turn ON / OFF Characteristics 10 Inductive Output Clamp 11 Maximum Load Inductance 12 Electrical Characteristics Power Stage 13 6 6.1 6.2 6.3 6.4 6.5 6.5.1 6.
Smart High-Side Power Switch BTS4130QGA Four Channel Device 1 Overview Basic Features • • • • • • • • • • • Withstand low Cranking Voltage Fit for 12V Application Four Channel device Very low Stand-by Current CMOS Compatible Inputs Electrostatic Discharge Protection (ESD) Optimized Electromagnetic Compatibility Logic ground independent from load ground Very low Leakage Current from OUT to the load in OFF State Green Product (RoHS compliant) AEC Qualified PG-DSO-20-32 Description The BTS4130QGA is a
BTS4130QGA Overview Diagnostic Feature • • • Open load detection in OFF state Feedback of the thermal shutdown in ON state Diagnostic feedback with open drain output Protection Functions • • • • • • • • Short circuit protection Overload protection Current limitation Thermal shutdown Overvoltage protection (including load dump) with external resistor Reverse battery protection with external resistor Loss of ground and loss of VS protection Electrostatic discharge protection (ESD) Application • All types
BTS4130QGA Block Diagram 2 Block Diagram Channel 0 VS voltage sensor internal power supply over temperature driver logic IN0 ESD protection T clamp for inductive load gate control & charge pump over current switch off OUT 0 open load detection ST 0/1 VS Channel 1 T IN1 Control and protection circuit equivalent to channel 0 OUT 1 Channel 2 VS voltage sensor internal power supply over temperature driver logic IN2 ESD protection T clamp for inductive load gate control & charge pump over
BTS4130QGA Pin Configuration 3 Pin Configuration 3.1 Pin Assignment Vs 1 20 Vs GND0/1 2 19 Vs IN0 3 18 OUT0 ST 0/1 4 17 OUT1 IN1 5 16 Vs GND2/3 6 15 Vs IN2 7 14 OUT2 ST2/3 8 13 OUT3 IN3 9 12 Vs Vs 10 11 Vs Pinout SO20 shared diag.vsd Figure 2 Pin Configuration 3.
BTS4130QGA Pin Configuration Pin Symbol Function 13 OUT3 Output 3; Protected High side power output channel 3 14 OUT2 Output 2; Protected High side power output channel 2 17 OUT1 Output 1; Protected High side power output channel 1 18 OUT0 Output 0; Protected High side power output channel 0 3.3 Voltage and Current Definition Figure 3 shows all terms used in this data sheet, with associated convention for positive values.
BTS4130QGA General Product Characteristics 4 General Product Characteristics 4.1 Absolute Maximum Ratings Absolute Maximum Ratings 1) TJ = 25°C; (unless otherwise specified) Pos. Parameter Symbol Limit values Unit Conditions Min. Max. -0.3 43 V – – 32 V – 0 20 V RECU = 20mΩ, RCable = 16mΩ/m, LCable = 1µH/m, Voltages 4.1.1 4.1.2 4.1.
BTS4130QGA General Product Characteristics Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. 4.2 Functional Range Tj = -40 °C to +150 °C; (unless otherwise specified) Pos. Parameter Symbol Limit values Min. Max. Unit Conditions 4.2.1 Operating Voltage VSOP 5.
BTS4130QGA Power Stage 5 Power Stage The power stages are built by an N-channel vertical power MOSFET (DMOS) with charge pump. 5.1 Output ON-State Resistance The ON-state resistance RDS(ON) depends on the supply voltage as well as the junction temperature Tj. Figure 4 shows the dependencies for the typical ON-state resistance. The behavior in reverse polarity is described in Chapter 6.4.
BTS4130QGA Power Stage 5.3 Inductive Output Clamp When switching OFF inductive loads with high side switches, the voltage VOUT drops below ground potential, because the inductance intends to continue driving the current. To prevent the destruction of the device due to high voltages, there is a voltage clamp mechanism implemented that keeps the negative output voltage at a certain level (VS-VDS(AZ)). Please refers to Figure 6 and Figure 7 for details.
BTS4130QGA Power Stage 5.3.1 Maximum Load Inductance During demagnetization of inductive loads, energy has to be dissipated in the BTS4130QGA. This energy can be calculated with following equation: V S – V DS ( AZ ) RL × IL L E = V DS ( AZ ) × ------- × ---------------------------------- × ln 1 – --------------------------------- + IL RL RL V S – V DS ( AZ ) Following equation simplifies under the assumption of RL = 0Ω.
BTS4130QGA Power Stage 5.4 Electrical Characteristics Power Stage Electrical Characteristics: Power stage VS = 12 V, Tj = -40 °C to +150 °C. Typical values are given at Tj = 25°C Pos. 5.4.1 Parameter ON-state resistance per channel Symbol RDS(ON) Limit values Min. Typ. Max. – 130 – Unit Conditions mΩ Tj = 25°C,1) IL = 2A, VIN = 5V, See Figure 4 A Tj = 150°C TA = 85°C1), Tj <150°C 52 V IDS = 40mA2) 1 5 µA VIN = 0V 0.
BTS4130QGA Protection Mechanisms 6 Protection Mechanisms The device provides embedded protective functions. Integrated protection functions are designed to prevent the destruction of the IC from fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are designed for neither continuous nor repetitive operation. 6.
BTS4130QGA Protection Mechanisms In the case the supply voltage is in between of VS(SC) max and VDS(AZ), the output transistor is still operational and follow the input. If at least one channel is in ON state, parameters are no longer warranted and lifetime is reduced compared to normal mode. This specially impacts the short circuit robustness, as well as the maximum energy EAS the device can handle. 6.
BTS4130QGA Protection Mechanisms 6.5.1 Current Limitation At first step, the instantaneous power in the switch is maintained to a safe level by limiting the current to the maximum current allowed in the switch IL(LIM). During this time, the DMOS temperature is increasing, which affects the current flowing in the DMOS. At thermal shutdown, the device turns OFF and cools down. A restart mechanism is used, after cooling down, the device restarts and limits the current to IL(SCR).
BTS4130QGA Protection Mechanisms 6.6 Electrical Characteristics Protection Functions Electrical Characteristics: Protection VS = 12 V, Tj = -40 °C to +150 °C. Typical values are given at Tj = 25°C Pos. Parameter Symbol Limit values Unit Conditions Min. Typ. Max. – – 2 mA VS = 32V VIN = 0V -VDS(REV) – 600 – mV IL= - 2A, Tj = 150°C VIN = 0V VS(AZ) 41 47 52 V Is = 40mA IL(LIM) – – 5 – 9 – 14 – – A Tj = -40°C, Tj = 25°C, Tj = 150°C – – 6.5 6.
BTS4130QGA Diagnostic Mechanism 7 Diagnostic Mechanism For diagnosis purpose, the BTS4130QGA provides status pin. 7.1 ST 0/1/2/3 Pin BTS4130QGA status pins are an open drain, active low circuit. Figure 12 shows the equivalent circuitry. As long as no “hard” failure mode occurs (Short circuit to GND / Over temperature or open load in OFF), the signal is permanently high, and due to a required external pull-up to the logic voltage will exhibit a logic high in the application.
BTS4130QGA Diagnostic Mechanism 7.2.1 Diagnostic in Open Load, Channel OFF For open load diagnosis in OFF-state, an external output pull-up resistor (ROL) is recommended. For calculation of the pull-up resistor value, the leakage currents and the open load threshold voltage VOL(OFF) has to be taken into account. Figure 13 gives a sketch of the situation and Figure 14 shows the typical timing diagram. Ileakage defines the leakage current in the complete system, including IL(OFF) (see Chapter 5.
BTS4130QGA Diagnostic Mechanism 7.2.2 ST 0/1 Signal in case of Over Temperature In case of over temperature, the junction temperature reaches the thermal shutdown temperature TjSC. In that case, the ST 0/1 signal is toggling between VST01(L) and VST01(H). Figure 15 gives a sketch of the situation. IN t V OUT t ST 0/1 t T JSC ∆T JSC TJ t Diagnostic In Overload shared toggling.vsd Figure 15 Sense signal in overtemperature condition . Data Sheet 20 Rev. 1.
BTS4130QGA Diagnostic Mechanism 7.3 Electrical Characteristics Diagnostic Functions Electrical Characteristics: Diagnostics VS = 12 V, Tj = -40 °C to +150 °C. Typical values are given at Tj = 25°C Pos. Parameter Symbol Limit values Unit Conditions Min. Typ. Max. VOL(OFF) 1.7 2.8 4.0 V – Status output (open drain) High level; Zener limit voltage VST (HIGH) 5.4 – – V IST= +1.6mA1), Status output (open drain) Low level VST (LOW) – – 0.6 V IST= +1.
BTS4130QGA Input Pins 8 Input Pins 8.1 Input Circuitry The input circuitry is CMOS compatible. The concept of the Input pin is to react to voltage transition and not to voltage threshold. With the Schmidt trigger, it is impossible to have the device in an un-defined state, if the voltage on the input pin is slowly increasing or decreasing. The output is either OFF or ON but cannot be in an linear or undefined state. The input circuitry is compatible with PWM applications.
BTS4130QGA Application Information 9 Application Information Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. VDD VBAT VDD Vdd Vs OUT IN0 OUT0 OUT IN1 OUT1 IN Microcontroller (e.g.
BTS4130QGA Package Outlines 1.27 8˚ ma x 7.6 -0.2 1) +0.09 0.35 x 45˚ 0.23 2.65 max 2.45 -0.2 Package Outlines 0.2 -0.1 10 0.4 +0.8 0.35 +0.15 2) 0.2 24x 20 10.3 ±0.3 0.1 11 GPS05094 1 12.8 1) 10 -0.2 Index Marking 1) Does not include plastic or metal protrusions of 0.15 max per side 2) Does not include dambar protrusion of 0.
BTS4130QGA Revision History 11 Revision History Version Date Changes 1.0 2008-03-18 Creation of the data sheet Data Sheet 25 Rev. 1.
Edition 2008-03-18 Published by Infineon Technologies AG 81726 Munich, Germany © 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics.
