User guide

Technical Description
Sealevel Systems PC-ACB.MP Page 3
Technical Description
The PC-ACB.MP utilizes the Zilog 85233 Enhanced Serial Communications Controller (ESCC). This chip features
programmable baud rate, data format and interrupt control. Refer to the ESCC Users Manual for details on
programming the 85233 ESCC chip.
Features
• One channel of synchronous or asynchronous communications using the Zilog Z85233 chip
• Programmable electrical interface selection EIA/TIA-232/530/530A/485 and ITU V.35
• Programmable options for Transmit clock as input or output
• Software programmable baud rate
Internal Baud Rate Generator
The baud rate of the ESCC is programmed under software control.
Control and Status Registers Definition
The control and status registers occupy 16 consecutive locations. The following tables provide a functional
description of the bit positions. X = do not care
Base Mode D7 D6 D5 D4 D3 D2 D1 D0
+4
RD 0 IRQST 0 0 0 0 0 DSRA
+4
WR X X X X X X X X
+5
RD 485CLK ECHOA SYNCA_RTS SYNCA_CTS AM3 AM2 AM1 AM0
+5
WR 485CLK ECHOA SYNCA_RTS SYNCA_CTS AM3 AM2 AM1 AM0
+6
RD 0 0 0 0 RLA LLA TSETSLA RXCOPTA
+6
WR X X X X RLA LLA TSETSLA RXCOPTA
+7
RD SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
Field Description
IRQST SCC interrupt status: 1 = No interrupt pending on ESCC 0 = Interrupt pending on ESCC.
DSRA DSRA: 1 = DSRA is not active 0 = DSRA is active
TSETSLA TSET clock source: 1 = Received TXC as source 0 = TRXCA as source
RXCOPTA RXCOPTA: 1 = Selects SCC PCLK for RTXCA 0 = Selects received RXC for
RTXCA
SYNCA_RTS SYNCA _RTS: 1 = SYNCA connected to RTS 0 = SYNCA is high
SYNCA_CTS SYNCA_CTS: 1 = SYNCA connected to CTS 0 = SYNCA is high
485CLK TSET switches with TXD 1 = clk switches 0 = no CLK switching
ECHOA ECHO enable: 1 = echo disabled 0 = echo enabled
AM0-AM3 I/O mode select. See table for valid interface options 0 = High Impedance
SD0-SD7 Optional security feature. Unique value per customer or application. Default value = FF
Note: Default values are listed in bold