Data Sheet

Ikalogic | SP209 series data sheet | 4
are later downloaded at a slower     
speed via the USB interface. This     
has the advantage of not being     
limited by USB transfer rate, but     
has the disadvantage of limited    
embedded memory.
● Streaming captured samples over   
the USB connection, at the    
maximum possible speed. While   
this offers the advantage of a     
virtually unlimited memory (only   
limited by host computer’s   
memory), it has the disadvantage    
of limiting the sampling rate to     
USB’s throughput.
SP209 combines the advantages of both     
streaming and embedded memory   
techniques. An embedded 2Gb DDR-3    
memory stores captured samples at 200     
MHz sampling rate on all channels, while      
a USB interface compresses and transfers     
the data simultaneously, effectively   
emptying the embedded memory and    
making more room for new samples.
This results is a logic analyzer that can       
capture dozens of minutes of logic signals      
activity on 9 channels at 200 MSPS.
Versatile trigger system
SP209 series offer a state of the art       
trigger system. It’s composed of two     
FlexiTrig ® trigger engines, each FlexiTrig     
engine can be used in one of those       
modes:
● Edge trigger
● Pulse trigger (with minimum and
maximum pulse width)
● Timed logic sequence
● Protocol based trigger (e.g. I2C bus
address or serial UART character)
● External trigger source
Furthermore, the two trigger engines    
(called A and B hereafter) can be      
cascaded in one of the following modes:
● A then B (Wait until A triggers then
arm B trigger engine)
● B then A
● A and B (Trigger engines A and B
must trigger, but in any order)
● A or B (whoever triggers first)
Finally, an external trigger output is     
always active, in all modes and generates      
a trigger pulse whenever a trigger     
condition is met and a capture starts.
Signal specifications for External trigger    
input and output are detailed in following      
section.
External trigger OUT specifications
There is an internal data path delay of       
20ns before external signals reach    
internal trigger engine (T0). When trigger     
event occurs, a 10ms (T2) pulse is      
generated on the Trig Out port. This port       
has a 50 Ω series impedance allowing      
easy interfacing to 50Ω input devices. This      
can be used to synchronise the capture      
with other equipment like an oscilloscope.     
Polarity of the trigger can be set in       
software. There is also a 10 ns delay (T1)        
between internal trigger detection and    
Trig Out assertion. Therefore, the total     
time for an external event to generate a       
Trigger OUT pulse is T0+T1 = 30ns.
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