User Manual

2.11.3 Parallel Bus Timing Diagram
Address
Data
Data
Address
Phase
Data
Phase
t1 t2
t3 t4
CLKOUTA
A12-A0
/CS
/RD
D7-D0
(Read)
/WR
D7-D0
(Write)
Address
Phase
Data
Phase
t1 t2
t3 t4
CLKOUTA
ARDY (Normally
Not-Ready System)
ARDY (Normally
Ready System)
Case 2
Case 4
Case 1
Case 3
t4
twt3t2
t4twtw
tw
t4tw
twt3
.
7521/2/2A/3/4/7 Series Hardware User’s Manual, Ver. 1.5 Sep/2002, 7Mh-001-15 -----61