User Manual

7521/2/2A/3/4/7 Series Hardware User’s Manual, Ver. 1.5 Sep/2002, 7Mh-001-15 -----60
JP2 pin definition & description:
No Name Description
1 A0
Address bus
2 D0
Data bus
3 A1
Address bus
4 D1
Data bus
5 A2
Address bus
6 D2
Data bus
7 A3
Address bus
8 D3
Data bus
9 A4
Address bus
10 D4
Data bus
11 A5
Address bus
12 D5
Data bus
13 A6
Address bus
14 D6
Data bus
15 A7 or N/C This pin is reserved & must be N/C for 7521 series
16 D7
Data bus
17 INT4 or N/C
Interrupt request input of channel 4(asynchronous, active high), this pin is
reserved & must be N/C for 7521 series
18 /WR
Write strobe output (synchronous, active low)
19 /CS
Chip select output (synchronous, active low)
20 /RD
Read strobe output (synchronous, active low)
• Address bus (output): A0 ~ A6, A7
• Data Bus (tri-state, bi-direction): D0 to D7
• INT4: leave this pin OPEN for no interrupt applications
• /CS, /RD, /WR: These 3 signals will be synchronous to CLOCKA (in JP1.3) & asynchronous to
ARDY (JP1.4)
• The CS\ will be active if program inport/outport from I/O address 0 to 0xff.
• The pin_15 & pin_17 are reserved by 7521 series; user must leave these two pins N/C for 7521
series.
Refer to “I/O Expansion Bus in the 7188X/7188E User’s Manual” for more
information.