User Manual

2.11.2 Definition
The definition of the I/O expansion bus is given as follows:
JP1 pin definition & description:
No Name Description
1 GND
Ground of PCB
2 GND
Ground of PCB
3 CLOCKA
Synchronous clock output of CPU
4 ARDY
Asynchronous ready input (level sensitive, OPEN=ready)
5 INT0
Interrupt request input of channel 0(asynchronous, active high)
6 INT1
Interrupt request input of channel 1(asynchronous, active high)
7 VCC
Power supply of PCB
8 RESET
Power up reset pulse (active high)
9 GND
Ground of PCB
10 /RESET
Power up reset pulse (active low)
11 TO_0
Timer output 0 of CPU (can be used as programmable D/I/O)
12 TO_1
Timer output 1 of CPU (can be used as programmable D/I/O)
13 TI_0
Timer input 0 of CPU (can be used as programmable D/I/O)
14 TI_1
Timer input 1 of CPU (can be used as programmable D/I/O)
15 SCLK
Common serial clock output of 7188 series
16 DIO9
Programmable D/I/O bit
17 DIO4
Programmable D/I/O bit
18 DIO14
Programmable D/I/O bit
19 VCC
Power supply of PCB
20 VCC
Power supply of PCB
• CLOCKA: 20.2752M for 7188XC, 40M for 7188XB & 7188XA
• ARDY: leave this pin OPEN for no wait states applications
• INT0, INT1: leave these two pins OPEN for no interrupt applications
• TO_0, TO_1: can be used as CPU’s timer output or programmable D/I/O
• TI_0, TI_1: can be used as CPU’s timer input or programmable D/I/O
• DIO4, DIO9, DIO14: programmable D/I/O bit
• SCLK: the 7188X/7188E series use this signal as a CLOCK source to drive all on-board
serial devices, so it is always programmed as D/O. Changing this signal to other
configurations will cause serious errors. User can use this signal to drive external serial
devices without any side effects.
7521/2/2A/3/4/7 Series Hardware User’s Manual, Ver. 1.5 Sep/2002, 7Mh-001-15 -----59