Datasheet

iC-LF1401
128x1 Linear Image Sensor
Rev A3, Page 7/9
DESCRIPTION OF FUNCTIONS
Normal operation
Following an internal power-on reset the integration
and hold capacitors are discharged and the sample
and hold circuit is set to sample mode. A high signal
at SI and a rising edge at CLK triggers a readout cycle
and with it a new integration cycle.
In this process the hold capacitors of pixels 1 to 127
are switched to hold mode immediately (SNH = 1),
with pixel 128 (SNH128 = 1) following suit one clock
pulse later. This special procedure allows all pixels to
be read out with just 128 clock pulses. The integration
capacitors are discharged by a one clock long reset
signal (NRCI = 0) which occurs between the 2
nd
and
3
rd
falling edge of the readout clock pulse (cf. Figure
4). After the 127 pixels have been read out these are
again set to sample mode (SNH = 0), likewise for pixel
128 one clock pulse later (SNH128 = 0).
SNH
SNH128
NRCI
integration time pixel 1−127
integration time pixel 128
Pix128
Pix127
...
Pix127 Pix128Pix126
127
Pix1
1
128
3
V(AO)
CLK
SI
Pix2 Pix3
126
1 2
127
128
2 4
...
Pix1
Figure 4: Readout cycle and integration sequence
If prior to the 128
th
clock pulse a high signal occurs
at SI the present readout is halted and immediately
reinitiated with pixel 1. In this instance the hold ca-
pacitors retain their old value i.e. hold mode prevails
(SNH/SNH128 = 0).
Pix2 Pix3
126
1
128
5
1
Pix4 Pix5
2 3
Pix2
4
Pix128
2
Pix1
...
...
SNH
SNH128
NRCI
2 4
Pix4Pix3
127
Pix127 Pix128
Pix126
Pix1Pix1
1
128
3
V(AO)
CLK
SI
Figure 5: Restarting a readout cycle
With more than 128 clock pulses until the next SI sig-
nal, pixel 1 is output without entering hold mode; the
output voltage tracks the voltage of the pixel 1 integra-
tion capacitor.