User manual

ManualsBrandsIBM ManualsOtherNetwork Card EM78P259N/260N

EM78P259N/260N

8-Bit Microprocessor

with OTP ROM

Product

Specification

DOC. VERSION 1.2

ELAN

MICROELECTRONICS CORP.

May 2007

Summary of content (89 pages)

PAGE 1
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Product Specification DOC. VERSION 1.2 ELAN MICROELECTRONICS CORP.
PAGE 2
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright © 2005~2007 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification.
PAGE 3
Contents Contents 1 2 3 4 5 General Description .................................................................................................. 1 Features ..................................................................................................................... 1 Pin Assignment ......................................................................................................... 2 Block Diagram ...............................................................................................
PAGE 4
Contents 6.2.13 6.2.14 6.2.15 6.2.16 6.2.17 6.2.18 6.2.19 IOC61 (TCCB Counter) ...................................................................................23 IOC71 (TCCBH/MSB Counter)........................................................................24 IOC81 (TCCC Counter)...................................................................................24 IOC91 (Low Time Register) .............................................................................25 IOCA1 (High Time Register).......
PAGE 5
Contents 6.11 Oscillator ......................................................................................................... 60 6.11.1 6.11.2 6.11.3 6.11.4 Oscillator Modes .............................................................................................60 Crystal Oscillator/Ceramic Resonators (Crystal) .............................................61 External RC Oscillator Mode ...........................................................................62 Internal RC Oscillator Mode .....
PAGE 6
Contents Specification Revision History Doc. Version Revision Description Date 1.0 Initial official version 2005/06/16 1.1 Added the IRC drift rate in the feature 2006/05/29 1. Improved the contents and format of the Features section, Fig.4-1 EM78P259N/260N Functional Block Diagram, Fig.6-2 TCC and WDT Block Diagram and Fig.6-11 IR/PWM System Block Diagram. 2. Modified Section 6.7 Analog-to-Digital Converter( ADC) 1.2 3. Modified Section 6.13.1 Code Option Register (Word 0) and Section 6.13.
PAGE 7
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 1 General Description The EM78P259N and EM78P260N are 8-bit microprocessors designed and developed with low-power and high-speed CMOS technology. The series has an on-chip 2K×13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides a protection bit to prevent intrusion of user’s code. Three Code option words are also available to meet user’s requirements.
PAGE 8
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 3 Pin Assignment (1) 18-Pin DIP/SOP P52/ADC2 (2) 20-Pin DIP/SOP/SSOP 1 18 P53/ADC3 2 17 P50/ADC0 P54/TCC/VREF 3 16 P55/OSCI 5 P60//INT 6 P61/TCCA 7 1 20 P57 2 19 P51/ADC1 P53/ADC3 3 18 P50/ADC0 P54/TCC/VREF 4 17 P55/OSCI 15 P70/OSCO 14 VDD 13 P67/IR OUT 12 P66/CIN- P62/TCCB 8 11 P65/CIN+ P63/TCCC 9 10 P64/CO /RESET 5 Vss 6 P60//INT 7 14 P67/IR OUT P61/TCCA 8 13 P66/CIN- P62/TCCB 9 12 P65/CIN+ P
PAGE 9
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 5 Pin Description 5.1 EM78P259NP/M Symbol Pin No.
PAGE 10
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 5.2 EM78P260NP/M/KM Symbol Pin No.
PAGE 11
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6 Function Description 6.1 Operational Registers 6.1.1 R0 (Indirect Address Register) R0 is not a physically implemented register. Its major function is to perform as an indirect address pointer. Any instruction using R0 as a pointer, actually accesses the data pointed by the RAM Select Register (R4). 6.1.
PAGE 12
EM78P259N/260N 8-Bit Microprocessor with OTP ROM "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to jump to any location within a page. "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page. "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top of stack.
PAGE 13
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.1.3.
PAGE 14
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.1.4 R3 (Status Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RST IOCS PS0 T P Z DC C Bit 7 (RST): Bit of reset type Set to “1” if wake-up from sleep on pin change, comparator status change, or AD conversion completed. Set to “0” if wake-up from other reset types Bit 6 (IOCS): Select the Segment of IO control register 0 = Segment 0 (IOC50 ~ IOCF0) selected 1 = Segment 1 (IOC51 ~ IOCC1) selected Bit 5 (PS0): Page select bits.
PAGE 15
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.1.6 R5 ~ R6 (Port 5 ~ Port 6) R5 & R6 are I/O registers The upper 2 bits of R5 are fixed to “0” (if EM78P259N is selected). Only the lower 6 bits of R5 are available (this applies to EM78P259N only as EM78P260N can use all the bits) 6.1.
PAGE 16
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Bit 3 & Bit 2 (RCM1, RCM0): IRC mode selection bits RCM 1 RCM 0 Frequency (MHz) 1 1 4 (default) 1 0 8 0 1 1 0 0 455kHz 6.1.8 R8 (AISR: ADC Input Select Register) The AISR register individually defines the pins of Port 5 as analog input or as digital I/O.
PAGE 17
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.1.9 R9 (ADCON: ADC Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VREFS CKR1 CKR0 ADRUN ADPD – ADIS1 ADIS0 Bit 7 (VREFS): Input source of the Vref of the ADC 0 = The Vref of the ADC is connected to Vdd (default value), and the P54/VREF pin carries out the function of P54 1 = The Vref of the ADC is connected to P54/VREF NOTE The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time.
PAGE 18
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Bit 1 ~ Bit 0 (ADIS1 ~ADIS0): Analog Input Select 00 = ADIN0/P50 01 = ADIN1/P51 10 = ADIN2/P52 11 = ADIN3/P53 These bits can only be changed when the ADIF bit (see Section 6.1.14, RE (Interrupt Status 2 & Wake-up Control Register)) and the ADRUN bit are both LOW. 6.1.
PAGE 19
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.1.12 RC (ADDATA1H: Converted Value of ADC) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 “0” “0” “0” “0” AD11 AD10 AD9 AD8 When AD conversion is completed, the result is loaded into the ADDATA1H. The ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 & Wake-up Control Register)) is set. RC is read only 6.1.
PAGE 20
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Bit 2 (CMPWE): Comparator wake-up enable bit 0 = Disable Comparator wake-up 1 = Enable Comparator wake-up When Comparator enters sleep mode, this bit must be set to “Enable.“ Bit 1 (ICWE): Port 5 input change to wake-up status enable bit 0 = Disable Port 5 input change to wake-up status 1 = Enable Port 5 input change to wake-up status When Port 5 change enters sleep mode, this bit must be set to “Enable“. Not implemented, read as ‘0’ Bit 0: 6.1.
PAGE 21
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.2 Special Purpose Registers 6.2.1 A (Accumulator) Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator, which is not an addressable register. 6.2.2 CONT (Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTE INT TS TE PSTE PST2 PST1 PST0 Note: The CONT register is both readable and writable Bit 6 is read only.
PAGE 22
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits PST2 PST1 PST0 TCC Rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Note: Tcc time-out period [1/Fosc x prescaler x 256 (Tcc cnt) x 1 (CLK=2)] Tcc time-out period [1/Fosc x prescaler x 256 (Tcc cnt) x 2 (CLK=4)] 6.2.
PAGE 23
EM78P259N/260N 8-Bit Microprocessor with OTP ROM TCCA signal source Bit 1 (TCCATS): 0 =: internal instruction cycle clock. P61 is a bi-directional I/O pin. 1 = transit through the TCCA pin TCCA signal edge Bit 0 (TCCATE): 0 = increment if transition from low to high takes place on the TCCA pin 1 = increment if transition from high to low takes place on the TCCA pin 6.2.
PAGE 24
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 0 = increment if the transition from low to high takes place on the TCCC pin 1 = increment if the transition from high to low takes place on the TCCC pin 6.2.6 IOCA0 (IR and TCCC Scale Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCCCSE TCCCS2 TCCCS1 TCCCS0 IRE HF LGP IROUTE Bit 7 (TCCCSE): Scale enable bit for TCCC An 8-bit counter is provided as scaler for TCCC and IR-Mode.
PAGE 25
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Bit 6 ~ Bit 4 (TCCCS2 ~ TCCCS0): TCCC scale bits The TCCCS2 ~ TCCCS0 bits of the IOCA0 register are used to determine the scale ratio of TCCC as shown below: Bit 3 (IRE): TCCCS2 TCCCS1 TCCCS0 TCCC Rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Infrared Remote Enable bit 0 = Disable IRE, i.e., disable H/W Modulator Function.
PAGE 26
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.2.
PAGE 27
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.2.9 IOCD0 (Pull-high Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 /PH57 /PH56 /PH55 /PH54 /PH53 /PH52 /PH51 /PH50 Note: The IOCD0 register is both readable and writable Bit 7 (/PH57): Control bit is used to enable the pull-high of the P57 pin (applicable to EM78P260N only). 0 = Enable internal pull-high; 1 = Disable internal pull-high.
PAGE 28
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Bit 5 (ADIE): ADIF interrupt enable bit 0 = disable ADIF interrupt 1 = enable ADIF interrupt Bit 4 (CMPIE): CMPIF interrupt enable bit.
PAGE 29
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Bit 5 (TCCCIE): TCCCIF interrupt enable bit 0 = Disable TCCCIF interrupt 1 = Enable TCCCIF interrupt Bit 4 (TCCBIE): TCCBIF interrupt enable bit 0 = Disable TCCBIF interrupt 1 = Enable TCCBIF interrupt Bit 3 (TCCAIE): TCCAIF interrupt enable bit 0 = Disable TCCAIF interrupt 1 = Enable TCCAIF interrupt Bit 2 (EXIE): EXIF interrupt enable bit 0 = Disable EXIF interrupt 1 = Enable EXIF interrupt Bit 1 (ICIE): ICIF interrupt enable bit 0 = Disable ICIF interr
PAGE 30
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.2.14 IOC71 (TCCBH/MSB Counter) The IOC71 (TCCBH) is an 8-bit clock counter for the most significant byte of TCCBX (TCCBH). It can be read, written, and cleared on any reset condition. When TCCBHE (IOC90) is “0,” then TCCBH is disabled. When TCCBHE is”1,” then TCCB is a 16-bit length counter.
PAGE 31
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.2.16 IOC91 (Low Time Register) The 8-bit Low time register controls the active or Low segment of the pulse. The decimal value of its contents determines the number of oscillator cycles and verifies that the IR OUT pin is active.
PAGE 32
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Bit 6 ~ Bit 4 (HTS2 ~ HTS0): High time scale bits: HTS2 HTS1 HTS0 High time Rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Bit 3 (LTSE): Low time scale enable bit. 0 = scale disable bit, Low time rate is 1:1 1 = scale enable bit, Low time rate is set as Bit 2~Bit 0.
PAGE 33
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.3 TCC/WDT and Prescaler There are two 8-bit counters available as prescalers that can be extended to 16-bit counter for the TCC and WDT respectively. The PST2 ~ PST0 bits of the CONT register are used to determine the ratio of the TCC prescaler, and the PWR2 ~ PWR0 bits of the IOCE0 register are used to determine the WDT prescaler. The prescaler counter is cleared by the instructions each time such instructions are written into TCC.
PAGE 34
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 1CLK (Fosc/1) 2 CLK (Fosc/2) 0 TCC Pin 1 8-Bit Counter (IOCC1) Data Bus MUX 8 to 1 MUX TE (CONT) TCC (R1) Prescaler TS (CONT) WDT 8-Bit counter 8 to 1 MUX TCC overflow interrupt PSR2~0 (CONT) Prescaler WDTE (IOCE0) WDT Time out PSW2~0 (IOCE0) Fig. 6-2 TCC and WDT Block Diagram 6.4 I/O Ports The I/O registers (Port 5, Port 6, and Port 7) are bi-directional tri-state I/O ports. Port 5 is pulled-high and pulled-down internally by software.
PAGE 35
EM78P259N/260N 8-Bit Microprocessor with OTP ROM PCRD Q _ Q PORT Q _ Q P R C L P R C L D PCWR CLK IOD D CLK PDWR PDRD 0 1 M U X Note: Open-drain is not shown in the figure. Fig. 6-3 I/O Port and I/O Control Register Circuit for Port 6 and Port 7 PCRD P Q R D _ CLK Q C L Q P R D _ CLK Q C L PORT Bit 6 of IOCE P R Q CLK _ C Q L D PCWR IOD PDWR 0 1 M U X PDRD INT Note: Open-drain is not shown in the figure. Fig.
PAGE 36
EM78P259N/260N 8-Bit Microprocessor with OTP ROM PCRD Q _ Q P50 ~ P57 Q PORT _ Q 0 P R D CLK PCWR C L P R C L IOD D CLK PDWR M U X 1 PDRD TI n D P R CLK C L Q _ Q Note: Pull-high (down) is not shown in the figure. Fig. 6-5 I/O Port and I/O Control Register Circuit for Port 50 ~ P57 I O C F.1 R F.1 TI 0 TI 1 …. TI 8 Fig. 6-6 Port 5 Block Diagram with Input Change Interrupt/Wake-up 30 • Product Specification (V1.2) 05.18.
PAGE 37
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.4.1 Usage of Port 5 Input Change Wake-up/Interrupt Function (1) Wake-up (2) Wake-up and Interrupt (a) Before Sleep (a) Before Sleep 1. Disable WDT 1. Disable WDT 2. Read I/O Port 5 (MOV R5,R5) 2. Read I/O Port 5 (MOV R5,R5) 3. Execute "ENI" or "DISI" 3. Execute "ENI" or "DISI" 4. Enable wake-up bit (Set RE ICWE =1) 4. Enable wake-up bit (Set RE ICWE =1) 5. Execute "SLEP" instruction 5.
PAGE 38
EM78P259N/260N 8-Bit Microprocessor with OTP ROM All I/O port pins are configured as input mode (high-impedance state) The Watchdog Timer and prescaler are cleared When power is switched on, the upper 3 bits of R3 is cleared The IOCB0 register bits are set to all "1" The IOCC0 register bits are set to all "1" The IOCD0 register bits are set to all "1" Bits 7, 5, and 4 of IOCE0 register is cleared Bit 5 and 4 of RE register is cleared RF and IOCF0 registers are cleared Executing the “SLEP
PAGE 39
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Case [c] If Comparator output status change is used to wake-up the EM78P259N/ 260N and CMPWE bit of the RE register is enabled before SLEP, WDT must be disabled by software. Hence, the EM78P259N/260N can be awakened only with Case 4. Wake-up time is dependent on the oscillator mode. In RC mode the Wake-up time is 32 clocks (for stable oscillators).
PAGE 40
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.5.1.1 Wake-Up and Interrupt Modes Operation Summary All categories under Wake-up and Interrupt modes are summarized below. Signal Sleep Mode Normal Mode DISI + IOCF0 (EXIE) Bit2=1 INT Pin Next Instruction + Set RF (EXIF)=1 N/A ENI + IOCF0 (EXIE) Bit2=1 Interrupt Vector (003H) + Set RF (EXIF)=1 RE (ICWE) Bit1=0, IOCF0 (ICIE) Bit1=0 IOCF0 (ICIE) Bit1=0 Oscillator, TCC, TCCX and IR/PWM are stopped. Port5 input status changed wake-up is invalid.
PAGE 41
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Signal Sleep Mode RE (CMPWE) Bit2=0, IOCE0 (CMPIE) Bit4=0 Normal Mode IOCF0 (CMPIE) Bit4=0 Comparator output status changed wake-up is invalid. Comparator output status change Oscillator, TCC, TCCX and IR/PWM are stopped. interrupted is invalid. RE (CMPWE) Bit2=0, IOCE0 (CMPIE) Bit4=1 N/A Set RE (CMPIF)=1, Comparator output status changed wake-up is invalid. N/A Oscillator, TCC, TCCX and IR/PWM are stopped.
PAGE 42
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.5.1.2 Register Initial Values after Reset The following summarizes the initialized values for registers.
PAGE 43
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Address N/A N/A Name IOCD0 (PHCR) IOCE0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name Reset Type /PH57 /PH56 /PH55 /PH54 /PH53 /PH52 /PH51 /PH50 Power-on 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-up from Pin Change P P P P P P P P Bit Name WDTC EIS ADIE CMPIE PSWE PSW2 PSW1 PSW0 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P
PAGE 44
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Address N/A N/A Name IOCA1 (HTR) IOCB1 (HLTS) Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name HTR7 HTR6 HTR5 HTR4 HTR3 HTR2 HTR1 HTR0 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name HTSE HTS2 HTS1 HTS0 LTSE LTS2 LTS1 LTS0 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P
PAGE 45
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Address 0x04 0x05 0x06 0x7 0x8 0x9 0xA 0XB Name R4(RSR) R5 R6 R7 R8 (AISR) R9 (ADCON) RA (ADOC) RB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name Reset Type X BS X X X X X X Power-on 0 0 U U U U U U /RESET and WDT 0 0 P P P P P P Wake-up from Pin Change 0 P P P P P P P Bit Name P57 P56 P55 P54 P53 P52 P51 P50 Power-on 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1
PAGE 46
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Address 0XC 0XD Name Reset Type RC (ADDATA1H) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name “0” “0” “0” “0” AD11 AD10 AD9 AD8 Power-on 0 0 0 0 U U U U /RESET and WDT 0 0 0 0 U U U U Wake-up from Pin Change 0 0 0 0 P P P P Bit Name AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Power-on U U U U U U U U U U U U U U U U P P P P P P P P Bit Name –- – ADIF CMPIF ADWE CMPWE ICWE
PAGE 47
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.5.2 The T and P Status under STATUS (R3) Register A reset condition is initiated by one of the following events: 1. Power-on reset 2. /RESET pin input "low" 3. WDT time-out (if enabled). The values of RST, T, and P as listed in the table below, are used to check how the processor wakes up.
PAGE 48
EM78P259N/260N 8-Bit Microprocessor with OTP ROM The external interrupt has an on-chip digital noise rejection circuit. Input pulse less than 8 system clock time is eliminated as noise. However, in Low Crystal oscillator (LXT) mode the noise rejection circuit is disabled. Edge selection is possible with INTE of CONT. When an interrupt is generated by the External interrupt (when enabled), the next instruction will be fetched from Address 003H. Refer to Word 1 Bits 9 & 8, Section 6.14.
PAGE 49
EM78P259N/260N 8-Bit Microprocessor with OTP ROM VCC P R CLK C L RF D /IRQn Q IRQn INT _ Q IRQm RFRD ENI/DISI Q IOCF _ Q P R C L IOD D CLK IOCFWR /RESET IOCFRD RFWR Fig. 6-8 Interrupt Input Circuit Interrupt sources ACC ENI/ DISI R3 Interrupt occurs RETI R4 STACKACC STACKR3 STACKR4 Fig. 6-9 Interrupt Backup Diagram In EM78P259N/260N, each individual interrupt source has its own interrupt vector as depicted in the table below.
PAGE 50
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.7 Analog-to-Digital Converter (ADC) The analog-to-digital circuitry consist of a 4-bit analog multiplexer; three control registers (AISR/R8, ADCON/R9, & ADOC/RA), three data registers (ADDATA/RB, ADDATA1H/RC, & ADDATA1L/RD), and an ADC with 12-bit resolution as shown in the functional block diagram below. The analog reference voltage (Vref) and the analog ground are connected via separate input pins.
PAGE 51
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Bit 1 (ADE1): AD converter enable bit of P51 pin 0 = Disable ADC1, P51 acts as I/O pin 1 = Enable ADC1 acts as analog input pin Bit 0 (ADE0): AD converter enable bit of P50 pin 0 = Disable ADC0, P50 acts as I/O pin 1 = Enable ADC0 acts as analog input pin 6.7.1.
PAGE 52
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Bit 4 (ADRUN): ADC starts to RUN. 0 = reset on completion of the conversion. This bit cannot be reset though software. 1 = an AD conversion is started. This bit can be set by software. Bit 3 (ADPD): ADC Power-down mode. 0 = switch off the resistor reference to save power even while the CPU is operating.
PAGE 53
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.7.2 ADC Data Register (ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD) When the AD conversion is completed, the result is loaded to the ADDATA, ADDATA1H and ADDATA1L registers. The ADRUN bit is cleared, and the ADIF is set. 6.7.3 ADC Sampling Time The accuracy, linearity, and speed of the successive approximation of AD converter are dependent on the properties of the ADC and the comparator.
PAGE 54
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 3. ADWE bit of the RE register is set to “1.” Wake-up from ADC conversion (where it remains in operation during sleep mode). 4. Wake-up and executes the next instruction if ADIE bit of IOCE0 is enabled and the “DISI” instruction is executed. 5. Wake-up and enters into Interrupt vector (Address 0x00C) if ADIE bit of IOCE0 is enabled and the “ENI” instruction is executed. 6.
PAGE 55
EM78P259N/260N 8-Bit Microprocessor with OTP ROM NOTE In order to obtain accurate values, it is necessary to avoid any data transition on the I/O pins during AD conversion. 6.7.6.2 Sample Demo Programs A. Define a General Register R_0 == 0 PSW == 3 PORT5 == 5 PORT6 == 6 R_E== 0XE ; Indirect addressing register ; Status register ; Interrupt status register B.
PAGE 56
EM78P259N/260N 8-Bit Microprocessor with OTP ROM RETI INITIAL: MOV A,@0B00000001 MOV AISR,A MOV A,@0B00001000 MOV ADCON,A ; To define P50 as an analog input ; To select P50 as an analog input channel, and AD power on ; To define P50 as an input pin and set clock rate at fosc/16 En_ADC: MOV A, @0BXXXXXXX1 ; To define P50 as an input pin, and the others IOW PORT5 ; are dependent on applications MOV A, @0BXXXX1XXX ; Enable the ADWE wake-up function of ADC, “X” by application MOV RE,A MOV A, @0BXXXX1XXX ; En
PAGE 57
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.8 Infrared Remote Control Application/PWM Waveform Generation 6.8.1 Overview This LSI can easily output infrared carrier or PWM standard waveform. As illustrated below, the IR and PWM waveform generation function include an 8-bit down count timer/counter, high time, low time, and IR control register.
PAGE 58
EM78P259N/260N 8-Bit Microprocessor with OTP ROM When an interrupt is generated by the High time down counter underflow (if enabled), the next instruction will be fetched from Address 018 and 01BH (High time and Low time, respectively). 6.8.2 Function Description The following figure shows LGP=0 and HF=1. The IROUT waveform modulates the Fcarrier waveform at low time segments of the pulse. Fcarrier low time width high time width low time width high time width HF start IRE IROUT Fig.
PAGE 59
EM78P259N/260N 8-Bit Microprocessor with OTP ROM The following figure shows LGP=0 and HF=1. The IROUT waveform modulates the Fcarrier waveform at low time segments of the pulse. When IRE goes low from high, the output waveform of IROUT will keep transmitting untill high time interrupt occurs. Fcarrier low time width high time width low time width HF high time width start IR disable IRE IROUT Always high- level Fig.
PAGE 60
EM78P259N/260N 8-Bit Microprocessor with OTP ROM The following figure shows LGP=1 and HF=1. When this bit is set to high level, the high time segment of the pulse is ignored. So, IROUT waveform output is determined by low time width. Fcarrier low time width HF low time width low time width high time width start IR disable IRE IROUT Always high-level Fig. 6-12e LGP=1 and HF=1, IROUT Pin Output Waveform 6.8.
PAGE 61
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Product Specification (V1.2) 05.18.
PAGE 62
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.9 Timer/Counter 6.9.1 Overview Timer A (TCCA) is an 8-bit clock counter. Timer B (TCCB) is a 16-bit clock counter. Timer C (TCCC) is an 8-bit clock counter that can be extended to 16-bit clock counter with programmable scalers. TCCA, TCCB, and TCCC can be read and written to, and are cleared at every reset condition. 6.9.
PAGE 63
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Under TCCBH / MSB Counter (IOC71): TCCBH/MSB (IOC71) is an 8-bit clock counter is for the most significant byte of TCCBX (TCCBH). It can be read, written to, and cleared on any reset condition. When TCCBHE (IOC90) is “0,” then TCCBH is disabled. When TCCBHE is”1,” then TCCB is a 16-bit length counter.
PAGE 64
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.9.3 Programming the Related Registers When defining TCCX, refer to its related registers operation as shown in the tables below.
PAGE 65
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.10.1 External Reference Signal The analog signal that is presented at Cin– compares to the signal at Cin+. The digital output (CO) of the comparator is adjusted accordingly by taking the following notes into considerations: NOTE ■ The reference signal must be between Vss and Vdd. ■ The reference voltage can be applied to either pin of the comparator. ■ Threshold detector applications may be of the same reference.
PAGE 66
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.10.3 Using a Comparator as an Operation Amplifier The comparator can be used as an operation amplifier if a feedback resistor is externally connected from the input to the output. In this case, the Schmitt trigger can be disabled for power saving purposes, by setting Bit 4, Bit 3 of the IOC80 register to <1,1>. See table under Section 6.2.4, IOC80 (Comparator and TCCA Control Registers) for Comparator/OP select bits function description.
PAGE 67
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.11 Oscillator 6.11.1 Oscillator Modes The EM78P259N/260N can be operated in four different oscillator modes, such as High Crystal oscillator mode (HXT), Low Crystal oscillator mode (LXT), External RC oscillator mode (ERC), and RC oscillator mode with Internal RC oscillator mode (IRC). You can select one of them by programming the OSC2, OCS1, and OSC0 in the Code Option register. The Oscillator modes defined by OSC2, OCS1, and OSC0 are described below.
PAGE 68
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.11.2 Crystal Oscillator/Ceramic Resonators (Crystal) The EM78P259N/260N can be driven by an external clock signal through the OSCI pin as illustrated below. OSCI EM78P259N EM78P260N OSCO Fig. 6-16 External Clock Input Circuit In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation. Fig. 6-17 below depicts such a circuit. The same applies to the HXT mode and the LXT mode.
PAGE 69
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Circuit diagrams for serial and parallel modes Crystal/Resonator: 330 330 C OSCI 7404 7404 7404 EM78P259N EM78P260N Crysta l Fig. 6-18 Serial Mode Crystal/Resonator Circuit Diagram 4.7K 7404 10K V dd O SC I EM 78P259N EM 78P260N 10K 7404 C rystal C1 10K C2 Fig. 6-19 Parallel Mode Crystal/Resonator Circuit Diagram 6.11.3 External RC Oscillator Mode For some applications that do not require precise timing calculation, the RC oscillator (Fig.
PAGE 70
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Based on the above reasons, it must be kept in mind that all supply voltage, the operation temperature, the components of the RC oscillator, the package types, and the way the PCB is layout, have certain effect on the system frequency. The RC Oscillator frequencies: Cext 20 pF 100 pF 300 pF Rext Average Fosc 5V, 25°C Average Fosc 3V, 25°C 3.3k 3.5 MHz 3.2 MHz 5.1k 2.5 MHz 2.3 MHz 10k 1.30 MHz 1.25 MHz 100k 140kHz 140kHz 3.3k 1.27 MHz 1.
PAGE 71
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.12 Power-on Considerations Any microcontroller is not warranted to start operating properly before the power supply stabilizes in its steady state. The EM78P259N/260N POR voltage range is 1.9V ~ 2.1V. Under customer application, when power is switched OFF, Vdd must drop below 1.9V and remains at OFF state for 10μs before power can be switched ON again. Subsequently, the EM78P259N/260N will reset and work normally.
PAGE 72
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.12.3 Residual Voltage Protection When the battery is replaced, device power (Vdd) is removed but the residual voltage remains. The residual voltage may trip below Vdd minimum, but not to zero. This condition may cause a poor power-on reset. Fig. 6-22 and Fig. 6-23 show how to create a protection circuit against residual voltage. Vdd Vdd EM78P259N EM78P260N 33K Q1 10K /RESET 100K 1N4684 Fig.
PAGE 73
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 6.13 Code Option EM78P259N/260N has two Code option words and one Customer ID word that are not part of the normal program memory. Word 0 Word1 Word 2 Bit12 ~ Bit0 Bit12 ~ Bit0 Bit12 ~ Bit0 6.13.1 Code Option Register (Word 0) Word 0 Bit 12 Bit 11 Bit 10 Bit 9 – – – Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 TYPE CLKS ENWDTB OSC2 OSC1 OSC0 HLP PR2 Bit 0 PR1 Bits 12 ~ 10: Not used (reserved).
PAGE 74
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Power consumption selection Bit 3 (HLP): 0 = Low power consumption, applies to working frequency at or below 4MHz 1 = High power consumption, applies to working frequency above 4MHz Bit 2 ~ 0 (PR2 ~ PR0): Protect Bits PR2 ~ PR0 are protect bits. Each protect status is as follows: PR2 PR1 PR0 Protect 1 Disable Others 1 Enable 1 6.13.
PAGE 75
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Bit 7 (WDTPS): WDT Time-out Period Selection bit Watchdog Time* WDT Time 1 18 ms 0 4.5 ms *These are theoretical values provided for reference only Instruction cycle selection bit Bit 6 (CYES): 0 = one instruction cycle. 1 = two instructions cycles (default) Bits 5, 4, 3, & Bit 2 (C3, C2, C1, C0): Calibrator of internal RC mode C3, C2, C1, & C0 must be set to “1” only (auto-calibration).
PAGE 76
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Convention: R = Register designator that specifies which one of the registers (including operation and general purpose registers) is to be utilized by the instruction. b = Bit field designator that selects the value for the bit located in the register R and which affects the operation.
PAGE 77
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Instruction Binary HEX Mnemonic Operation Status Affected 0 0101 01rr rrrr 05rr INC R R+1 → R Z 0 0101 10rr rrrr 05rr DJZA R R-1 → A, skip if zero None 0 0101 11rr rrrr 05rr DJZ R R-1 → R, skip if zero None 0 0110 00rr rrrr 06rr RRCA R R(n) → A(n-1),R(0) → C, C → A(7) C 0 0110 01rr rrrr 06rr RRC R R(n) → R(n-1),R(0) → C, C → R(7) C 0 0110 10rr rrrr 06rr RLCA R R(n) → A(n+1),R(7) → C, C → A(0) C 0 0110 11rr rrrr 06rr RLC R
PAGE 78
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 8 DC Electrical Characteristics Ta=25 °C, VDD=5.0V±5%, VSS=0V Symbol Parameter Crystal: VDD to 5V Fxt Crystal: VDD to 3V ERC: VDD to 5V VIHRC VILRC IIL VIH1 VIL1 VIHT1 VILT1 VIHT2 VILT2 VIHX1 VILX1 IOH1 IOH2 IOL1 IOL2 Input High Threshold Voltage (Schmitt trigger) Input Low Threshold Voltage (Schmitt trigger) Input Leakage Current for input pins Input High Voltage Condition Min Two cycles with two clocks R: 5.
PAGE 79
EM78P259N/260N 8-Bit Microprocessor with OTP ROM Symbol ICC1 ICC2 ICC3 ICC4 Parameter Condition at two clocks (VDD to 3V) at two clocks (VDD to 3V) Unit (Crystal type,CLKS="0"), output 15 20 μA 15 25 μA 1.9 2.2 mA 3.0 3.
PAGE 80
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 8.1 AD Converter Characteristics Vdd=2.5V to 5.5V, Vss=0V, Ta=25°C Symbol VAREF VASS VAI Parameter Analog reference voltage Condition VAREF - VASS ≥ 2.5V Analog input voltage Typ. Max. Unit 2.5 – Vdd V Vss – Vss V VASS – VAREF V Analog supply current Vdd=VAREF=5.0V, VASS =0.0V (V reference from Vdd) 750 850 1000 uA –10 0 +10 uA Analog supply current Vdd=VAREF=5.0V, VASS=0.
PAGE 81
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 8.2 Comparator (OP) Characteristics Vdd = 5.0V, Vss=0V, Ta=25°C Symbol Parameter Condition Min. Typ. Max. Unit - 0.1 0.2 - V/us - - - 30 mV Vdd =5.0V, VSS =0.0V 0 5 V SR Slew rate Vos Input offset voltage IVR Input voltage range OVS Output voltage swing Vd =5.0V, VSS =0.0V, RL=10KΩ 0 0.2 0.3 4.7 4.
PAGE 82
EM78P259N/260N 8-Bit Microprocessor with OTP ROM IRC OSC Frequency (VDD=5V) 10 9 Frequency (M Hz) 8 7 6 5 4 3 2 1 0 -40 -20 0 25 50 70 85 Temperature (℃) Fig. 8-2 Internal RC OSC Frequency vs.
PAGE 83
EM78P259N/260N 8-Bit Microprocessor with OTP ROM 10 Timing Diagrams AC Test Input/Output Waveform VDD-0.5V 0.75VDD TEST POINTS 0.25VDD 0.75VDD 0.25VDD GND+0.5V AC Testing : Input is driven at VDD-0.5V for logic "1",and GND+0.5V for logic "0".Timing measurements are made at 0.75VDD for logic "1",and 0.25VDD for logic "0". RESET Timing (CLK="0") NOP Instruction 1 Executed CLK /RESET Tdrh TCC Input Timing (CLKS="0") Tins CLK TCC Ttcc Product Specification (V1.2) 05.18.
PAGE 84
EM78P259N/260N 8-Bit Microprocessor with OTP ROM APPENDIX A Package Type OTP MCU Package Type Pin Count Package Size EM78P259NPS/NPJ DIP 18 300mil EM78P259NMS/NMJ SOP 18 300mil EM78P260NPS/NPJ DIP 20 300mil EM78P260NMS/NMJ SOP 20 300mil SSOP 20 209mil EM78P260NKMS/NKMJ B Package Information B.1 18-Lead Plastic Dual in line (PDIP) — 300 mil eB θ Symbal A A1 A2 c D E1 E eB B B1 L e θ Min 0.381 3.175 0.203 Normal Max 4.450 3.302 0.254 3.429 0.356 22.610 6.220 7.370 8.510 0.
PAGE 85
EM78P259N/260N 8-Bit Microprocessor with OTP ROM B.2 18-Lead Plastic Small Outline (SOP) — 300 mil Symbal Min Normal A 2.350 A1 0.102 b 0.406(TYP) c 0.230 E 7.400 H 10.000 D 11.350 L 0.406 0.838 e 1.27(TYP) θ b 0 Max 2.650 0.300 0.320 7.600 10.650 11.750 1.270 8 e c TITLE: SOP-18L(300MIL) PACKAGE OUTLINE DIMENSION File : Edtion: A SO18 Unit : mm Scale: Free Material: Sheet:1 of 1 Product Specification (V1.2) 05.18.
PAGE 86
EM78P259N/260N 8-Bit Microprocessor with OTP ROM b Symbal A A1 A2 b c E E1 D L L1 e E E1 B.3 20-Lead Plastic Shrink Small Outline (SSOP) — 209 mil θ e Min 0.050 1.620 0.220 0.090 Normal 1.750 7.400 5.000 6.900 0.650 7.800 5.300 7.200 0.750 1.250(REF ) 0.650(TYP) 0 4 Max 2.130 0.250 1.880 0.380 0.200 8.200 5.600 7.500 0.
PAGE 87
EM78P259N/260N 8-Bit Microprocessor with OTP ROM B.4 20-Lead Plastic Dual-in-line (PDIP) — 300 mil E Symbal A A1 A2 c D E1 E eB B B1 L e 0.381 3.175 0.203 Normal Max 4.450 3.302 0.254 3.429 0.356 25.883 6.220 7.370 8.510 0.356 1.143 26.060 26.237 6.438 6.655 7.620 7.870 9.020 9.530 0.457 0.559 1.524 1.778 3.048 3.302 3.556 2.540(TYP) 0 15 A1 A2 θ Min TITLE: PDIP-20L 300MIL PACKAGE OUTLINE DIMENSION File : D20 Edtion: A Unit : mm Scale: Free Material: Sheet:1 of 1 Product Specification (V1.
PAGE 88
EM78P259N/260N 8-Bit Microprocessor with OTP ROM B.5 20-Lead Plastic Small Outline (SOP) — 300 mil Symbal A A1 b c E H D L e θ b Min Normal 2.350 0.102 Max 2.650 0.300 0.406(TYP) 0.230 7.400 10.000 12.600 0.630 0 0.838 1.27(TYP) 0.320 7.600 10.650 12.900 1.100 8 e c TITLE: SOP-20L(300MIL) PACKAGE OUTLINE DIMENSION File : Edtion: A SO20 Unit : mm Scale: Free Material: Sheet:1 of 1 82 • Product Specification (V1.2) 05.18.
PAGE 89
EM78P259N/260N 8-Bit Microprocessor with OTP ROM C Quality Assurance and Reliability Test Category Test Conditions Remarks Solder temperature=245±5°C, for 5 seconds up to the stopper using a rosin-type flux Solderability Step 1: TCT, 65°C (15mins)~150°C (15mins), 10 cycles Step 2: Bake at 125°C, TD (durance)=24 hrs Step 3: Soak at 30°C/60%，TD (durance)=192 hrs Pre-condition Step 4: IR flow 3 cycles (Pkg thickness ≥ 2.