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EM78P221/2N

8-Bit Microcontroller

with OTP ROM

Product

Specification

DOC. VERSION 1.0

ELAN

MICROELECTRONICS CORP.

October 2007

Summary of content (70 pages)

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EM78P221/2N 8-Bit Microcontroller with OTP ROM Product Specification DOC. VERSION 1.0 ELAN MICROELECTRONICS CORP.
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Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright © 2007 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification.
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Contents Contents EM78P221/2N-V Package version.................................................................................... 1 EM78P221/2N-U Package version ................................................................................... 1 1 General Description .................................................................................................. 2 2 Features .....................................................................................................................
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Contents 6.2.27 6.2.28 6.2.29 6.2.30 6.2.31 6.2.32 6.2.33 6.2.34 Bank 2-R8 (Operating Mode Control Register).................................................19 Bank 2-R9~RF (Reserve)..................................................................................19 Bank 3-R5 (Timer Clock/Counter) .....................................................................19 Bank 3-R6 (IRC Control)-only for ICE ...............................................................
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Contents 7 8 Absolute Maximum Ratings ................................................................................... 53 DC Electrical Characteristics ................................................................................. 53 9 10 8.1 Comparator (OP) Characteristic ....................................................................... 55 AC Electrical Characteristic ................................................................................... 55 Timing Diagrams .....................
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Contents Specification Revision History Doc. Version vi • Revision Description Date 0.9 Preliminary version 2007/03/20 1.0 Initial released version 2007/10/19 Product Specification (V1.0) 10.19.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM Read Me First ! Comparison between V-Package and U-Package version This series of microcontrollers comprise of the older V-package version and the newer U-package version. In the newer U-package version, a Code Option NRM is added and various features such as Crystal mode Operating frequency range, IRC mode wake-up time, WDT Time-out time, Comparator function and Pins function have been modified to favorably meet users’ requirements.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 1 General Description EM78P221N and EM78P222N are 8-bit microprocessors designed and developed with low-power and high-speed CMOS technology. Each device in the series has as an on-chip 4K×13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). Each provides a protection bit to prevent intrusion of user’s OTP memory code. Two Code option bits are also available to meet user’s requirements.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 3 Pin Assignment (1) 28-Pin DIP/SOP/SSOP (2) P55 1 28 P56/TCC 2 27 P53/OSCI VDD 3 26 P52/OSCO P81//RESET 1 24 P81//RESET 2 23 P53/OSCI P72/CIN+ VDD 3 22 P52/OSCO 22 P73/CIN- VSS 4 21 P70 21 P67 20 P71/CO/INT1 19 P72/CIN+ 18 P73/CIN- 25 P70 5 24 P71/CO/INT1 P60 6 23 7 P62 8 P63 9 EM78P222N 4 20 P77/INT0 5 P60 6 P61 7 EM78P221N P55 P56/TCC VSS P77/INT0 P61 24-Pin DIP/SOP/SSOP P64 10 19 P66 P65
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 4 Pin Description 4.1 EM78P222N Symbol P50~P57 P60~P67 6 ~ 10 19 ~21 P70~ P77 5 14 ~ 16 22~25 Type Function I/O 8-bit General purpose input/output pins Default value at power-on reset I/O 8-bit General purpose input/output pins Default value at power-on reset I/O 8-bit General purpose input/output pins Default value at power-on reset. P72 and P73 are open drain pins when used as output pins in ICE220N simulator.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 4.2 EM78P221N Symbol Pin No. Type P50~P57 1~2 11~14 22~23 I/O 8-bit General purpose input/output pins Default value at power-on reset.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 5 Block Diagram ROM PC Instruction Register 8-level stack (13 bit) Ext. OSC. Int. RC Ext. RC P8 P80 P81 Oscillation Generation P7 Reset P70 P71 P72 P73 P74 P75 P76 Instruction Decoder WDT TCC Port change TCC Port 6 Mux . ALU P77 P6 P60 P61 P62 P63 P64 P65 P66 P67 R4 RAM ACC R3 (Status Reg.) Interrupt Control Register LVR P5 P50 P51 P52 P53 P54 P55 P56 P57 Interrupt Circuit Comparator Ext INT Cin+ Cin- CO Fig.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6 Function Description 6.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.2 Registers Description 6.2.1 A (Accumulator) Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator. The Accumulator is not an addressable register. 6.2.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.2.3 R0 (Indirect Addressing Register) R0 is not a physically implemented register. Its major function is to perform as an indirect address pointer. Any instruction using R0 as a pointer, actually accesses the data pointed by the RAM Select Register (R4). 6.2.4 R1 (Memory Switch Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 “0” “0” “0” “0” “0” “0” BS1 BS0 Bits 7~2: not used bits, fixed to 0 all the time.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to jump to any location within a Page (1K). "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page (1K). "LJMP" instruction allows direct loading of the lower 11 program counter bits.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.2.7 R4 (Select Indirect Address) Bits 7~6: not used, fixed to 0 all the time. Bit 5 ~ Bit 0: used to select registers (Address: 00 ~ 3F) in indirect addressing mode. 6.2.8 Bank 0-R5 (Port 5) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P57 P56 P55 P54 P53 P52 P51 P50 Bits 7 ~ 0 (P57 ~ P50): I/O data bits 6.2.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.2.13 Bank 0-RE (WUCR: Wake-up Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EX1IF 0 0 ICWE 0 CMPWE 0 CMPIF Bit 7 (EX1IF): External interrupt flag. Set by INT1 pin, reset by software.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM Bit 1 (ICIF): Port 6 input status change interrupt flag. Set when Port 6 input changes. Reset by software. 0 = no interrupt occurs 1 = with interrupt request Bit 0 (TCIF): TCC overflow interrupt flag. Set when TCC overflows. Reset by software. 0 = no interrupt occurs 1 = with interrupt request NOTE ■ Bank 0-RF <2, 1, 0> can be cleared by instruction but cannot be set. ■ Bank1-RF <2, 1, 0> is an interrupt mask register.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.2.17 Bank 1-R9 (Reserve) Bits 7~0: not used, fixed to 0 all the time 6.2.18 Bank 1-RA (CMPCON: Comparator Control Register) Bit 7 Bit 6 EIS1 EIS0 Bit 7 (EIS1): Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 CMPOUT CMPCOS1 CMPCOS0 Control bit used to define the function of the P71 (/INT1) pin 0 = P71, normal I/O pin 1 = /INT1, external interrupt pin.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.2.19 Bank 1-RB (Pull-down Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 /PD7 /PD6 /PD5 /PD4 /PD3 /PD2 /PD1 /PD0 Bank 1-RB register is both readable and writable Bit 7 (/PD7): Control bit used to enable the pull-down function of the P67 pin 0 = Enable internal pull-down function 1 = Disable internal pull-down function Bit 6 (/PD6): Control bit used to enable the pull-down function of the P66 pin.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.2.21 Bank 1-RD (Pull-high Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 /PH7 /PH6 /PH5 /PH4 /PH3 /PH2 /PH1 /PH0 Bank 1-RD register is both readable and writable. Bit 7 (/PH7): Control bit used to enable the pull-high function of the P67 pin. 0 = Enable internal pull-high 1 = Disable internal pull-high Bit 6 (/PH6): Control bit used to enable the pull-high function of the P66 pin.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM Bit 4 ~ Bit 2 (PSW2 ~ PSW0): WDT prescaler bits PSW2 0 0 0 0 1 1 1 1 PSW1 0 0 1 1 0 0 1 1 PSW0 0 1 0 1 0 1 0 1 WDT Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 Bit 0 (CMPIE): CMPIF interrupt enable bit 0 = Disable CMPIF interrupt 1 = Enable CMPIF interrupt When the Comparator output status change is used to enter an interrupt vector or to enter next instruction, the CMPIE bit must be set to “Enable“.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.2.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.2.26 Bank 2-R7 (HSCR2: High Sink Control Register for Port 6) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HS67 HS66 HS65 HS64 HS63 HS62 HS61 HS60 [With Simulator]: function nonexistent [With EM78P221/2N]: General I/O pins.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.2.30 Bank 3-R6 (IRC Control)-only for ICE Bit 7 6 5 4 3 2 1 0 EM78P221/2N ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ICE220N C3 C2 C1 C0 RCM1 RCM0 ‘0’ ‘0’ Bits 7 ~ 2: [With Simulator (C3~C0, RCM1~RCM0)]: IRC calibration bits in IRC oscillator mode. In IRC oscillator mode of ICE220N simulator, these are the IRC mode selection bits and IRC calibration bits. [With EM78P221/2N]: Unimplemented, read as ‘0’.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.2.31 Bank 3-R7 (Noise and LVR Control) - only for ICE Bit 7 6 5 4 3 2 1 0 EM78P221/2N ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ICE220N “0” “0” “0” “0” NRHL NRE LVR1 LVR0 Bits 7 ~ 4: not used, fixed to "0" all the time. Bits 3 ~ 0: [With EM78P221/2N]: Unimplemented, read as ‘0’. [With Simulator]: Bit 3 (NRHL): Noise rejection high/low pulses define bit.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.3 TCC/WDT and Prescaler There are two 8-bit counters available as prescalers for the TCC and WDT. The PST0~PST2 bits of the CONT register are used to determine the ratio of the TCC prescaler, and the PWR0~PWR2 bits of the Bank 1-RE register are used to determine the WDT prescaler. The prescaler counter is cleared by the instructions each time such instructions are written into TCC. The WDT and prescaler are cleared by the “WDTC” and “SLEP” instructions. Fig.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM CLK (Fosc) 0 TCC Pin 8-bit Counter Data Bus 8 to 1 MUX TCC (R1) MUX 1 TE (CONT) Prescaler TS (CONT) WDT TCC overflow Interrupt PSR2~0 (CONT) 8-bit Counter 8 to 1 MUX Prescaler WDTE (Bank 1-RE) PSW2~0 (Bank 1-RE) WDT Time out Fig. 6-2 TCC and WDT Block Diagram 6.4 I/O Ports The I/O registers (Port 5, Port 6, Port 7, and Port 8) are bidirectional tri-state I/O ports.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM PCRD P R Q _ Q PCWR C L P77, /INT0 P71, /INT1 P R Q PORT D CLK _ D CLK Q IOD PDWR C L EIS1,EIS0 D P R CLK C L M U X 0 Q 1 _ Q PDRD INT Note: CO2, Pull-high and Open-drain are not shown in the figure. Fig.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM ICIE D P R Q Interrupt CLK _ C Q L RE.1 ENI Instruction P D R Q T10 T11 CLK _ C Q L P Q R D CLK _ Q C L T17 DISI Instruction Interrupt (Wake-up from SLEEP) /SLEP ICWE Next Instruction (Wake-up from SLEEP) Fig. 6-6 Port 6 Block Diagram with Input Change Interrupt/Wake-up 6.4.1 Usage of Port 6 Input Change Wake-up/Interrupt Function Usage of Port 6 Input Status Change Wake-up/Interrupt (1) Wake-up (a) Before Sleep 1. Disable WDT 2.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.5 Reset and Wake-up 6.5.1 Reset and Wake-up Operation A reset is initiated by one of the following events: 1. Power-on reset 2. /RESET pin input "low" 3. WDT time-out (if enabled) A device is kept in a reset condition for a duration of approximately 18ms 2 after the reset is detected. When in LXT mode, the reset time is 500ms.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM The first two cases (1 & 2) will cause the EM78P221/2N to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). Cases 3 & 4 are considered the continuation of program execution and the global interrupt ("ENI" or "DISI" being executed) decides whether or not the controller branches to the interrupt vector following a wake-up.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM If Port 6 Input Status Change Interrupt is used to wake up the EM78P221/2N (as in Case b above), the following instructions must be executed before SLEP: MOV A, @000110xxb BANK 1 MOV RE, A WDTC BANK 0 MOV R6, R6 ENI (or DISI) MOV A, @xxx1xxxxb MOV RE MOV A, @00000x1xb BANK 1 MOV RF, A SLEP ; Select WDT prescaler and disable WDT ; Clear WDT and prescaler ; Read Port 6 ; Enable (or disable) global interrupt ; Enable Port 6 input change wake-up bit ; Enable Por
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EM78P221/2N 8-Bit Microcontroller with OTP ROM The controller can be awakened from sleep mode and idle mode. The wake-up signals are listed as follows: Signal INT0 INT1 Port 6 Input Status Change Normal Mode N/A DISI + Bank 1-RF (EXIE) Bit 2 = 1 Next Instruction+ Set Bank 0-RF (EX0IF) = 1 or Set Bank 0-RE (EX1IF) = 1 ENI + Bank 1-RF (EXIE) Bit 2 = 1 Interrupt Vector (0x08)+ Set Bank 0-RF (EX0IF) = 1 Bank 0-RE (ICWE) Bit 4 = 0, Bank 1-RF (ICIE) Bit 1 = 0 Oscillator, TCC and TCC are stopped.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.5.1.2 Register Initial Values after Reset The following table summarizes the registers initialized values.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P77 P76 P75 P74 P73 P72 P71 P70 U U U U U U U U U U U U U U U U Wake-up from Pin Change P P P P P P P P Bit Name - - NREN - - - P81 P80 0 0 0 0 0 0 U U 0 0 0 0 0 0 U U Wake-up from Pin Change P P P P P P P P Bit Name - - - - - - - - Power-on 0 0 0 0 0 0 0 0 /RESET & WDT 0 0 0 0 0 0 0 0
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EM78P221/2N 8-Bit Microcontroller with OTP ROM Address 0x8 0x9 0xA 0xB 0xC 0xD 0xE 32 • Name Bank 1-R8 Bank 1-R9 (Reserve) Bank 1-RA (CMPCON) Bank 1-RB Bank 1-RC Bank 1-RD Bank 1-RE Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Bit Name - - - C81 C80 Power-on 0 0 0 1 0 1 0 1 0 1 1 /RESET & WDT 0 0 0 1 0 1 0 1 0 1 1 Wake-up from Pin Change P P P P P P P P P P P Bit Name - - - - - - - - Power-on 0 0 0 0 0 0 0 0 /RESET & WDT
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EM78P221/2N 8-Bit Microcontroller with OTP ROM Address 0xF 0x05 0x06 0x07 0x8 0x9 ~ 0xF 0x05 0x06 Name Bank 1-RF Bank 2-R5 (HDCR) Bank 2-R6 (HSCR1) Bank 2-R7 (HSCR2) Bank 2-R8 (OMCR) Bank 2-R9 (RF) Bank 3-R5 (TCC) Bank 3-R6 (IRC) (only for ICE) Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name - - - - - EXIE ICIE TCIE Power-on 0 0 0 0 0 0 0 0 /RESET & WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name HD67
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EM78P221/2N 8-Bit Microcontroller with OTP ROM Address 0x07 Reset Type Name Bank 3-R7 (only for ICE) 0x10 ~ R10 ~ R1F 0x1F 0x20 ~ Bank 0~3 0x3F R20 ~ R3F Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name - - - - NRHL NRE LVR1 LVR0- Power-on U U U U 1 1 1 1 /RESET & WDT P P P P 1 1 1 1 Wake-up from Pin Change P P P P P P P P Bit Name - - - - - - - - Power-on U U U U U U U U /RESET & WDT P P P P P P P P Wake-up from Pin Chang
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.5.2 The T and P Status under Status Register A reset condition is initiated by one of the following events: 1. Power-on reset 2. /RESET pin input "low" 3. WDT time-out (if enabled) The values of T and P as listed in the table below, are used to check how the processor wakes up.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.6 Interrupt The EM78P221/2N has four interrupts as listed below: 1. TCC overflow interrupt 2. Port 6 Input Status Change Interrupt 3. External interrupt INT0, INT1 4. When the Comparator 1 output status changes Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g., "MOV R6, R6") is necessary. Each Port 6 pin will have this feature if its status changes.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM BANK0-RE/RF RD BANK0-RE/RF BANK1-RE/RF WR BANK1-RE/RF BANK1-RE/RF RD BANK0-RE/RF WR Fig. 6-8 Interrupt Input Circuit ACC Interrupt Sources R1 (5, 4 ,1 ,0) ENI/DISI R3 (2 ~0) R4 Interrupt Stack ACC occurs Stack R1 RETI Stack R3 Stack R4 Fig. 6-9 Interrupt Backup Diagram Product Specification (V1.0) 10.19.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.7 Comparator The EM78P221/2N has one comparator comprising of two analog inputs and one output. The comparator can be utilized to wake up the EM78P221/2N from sleep mode. The comparator circuit diagram is depicted in the figure below. Cin - CO CMP Cin+ + 10mV Cin Cin+ 10mV Output Fig. 6-10 Comparator Circuit Diagram & Operating Mode 6.7.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM NOTE ■ The highest priority of P71/INT1/CO is INT1. When EIS1=0, the working type of P71/INT1/CO is determined by CMPCOS1 and CMPCOS2. ■ The CO and P71of the P71/CO pins cannot be used at the same time. ■ The P71/CO pin priority is as follows: High P71/INT1/CO Pin Priority Medium Low /INT1 CO P71 The following figure shows the Comparator Output block diagram.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.7.3.2 Bank 1-RA (CMPCON: Comparator Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EIS1 EIS0 CMPOUT CMPCOS1 CMPCOS0 0 0 0 Bit 5 (CMPOUT): The result of the Comparator output Bit 4 ~ Bit 3 (CMPCOS1 ~ CMPCOS0): Comparator Select bits CMPCOS1 CMPCOS0 Function Description 0 0 Comparator is not used.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.8 Oscillator 6.8.1 Oscillator Modes The EM78P221/2N can be operated in six different oscillator modes, such as High Crystal oscillator mode (HXT 1, 2), Low Crystal oscillator mode (LXT 1, 2), External RC oscillator mode (ERC), and RC oscillator mode with Internal RC oscillator (IRC). Select one of such modes by programming the OSC2, OCS1, and OSC0 in the Code Option register. The Oscillator modes defined by OSC2, OCS1, and OSC0 are described below.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation. Fig. 6-13 below depicts such a circuit. The same applies to the HXT 1, 2 modes and the LXT 1, 2 modes. C1 OSCI Crystal OSCO RS C2 Fig. 6-13 Crystal/Resonator Circuit The following table provides the recommended values for C1 and C2.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM Fig. 6-13-1 Parallel Mode Crystal/Resonator Circuit Diagram Product Specification (V1.0) 10.19.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.8.3 External RC Oscillator Mode For some applications that do not require precise timing calculation, the RC oscillator (Fig. 6-14) could offer a cost-effective oscillator configuration. Nevertheless, it should be noted that the frequency of the RC oscillator is influenced by the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even by the operation temperature.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.8.4 Internal RC Oscillator Mode The EM78P221/2N offers a versatile internal RC mode with default frequency value of 4MHz. Internal RC oscillator mode has other frequencies (1MHz, 16MHz, and 455kHz) that can be set by Code Option (Word 1), RCM1, and RCM0. The Table below describes the EM78P221/2N internal RC drift with the variations on voltage, temperature, and process. Internal RC Drift Rate (Ta=25°C, VDD=5.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.9.2 Residual Voltage Protection When the battery is replaced, device power Vdd is removed but residual voltage remains. The residual voltage may trip below Vdd minimum, but not to zero. This condition may cause a poor power-on reset. Fig. 6-16 and Fig. 6-17 show how to create a protection circuit against residual voltage. VDD VDD 33K Q1 10K /RESET 100K 1N4684 Fig. 6-16 Residual Voltage Protection Circuit 1 VDD VDD R1 Q1 /RESET R3 R2 Fig.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM LVR characteristics are set at Code Option Word 0, Bits 10 and 9. Detailed operation mode is as follows: Word 0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TYPE1 TYPE0 LVR1 LVR0 CLKS ENWDTB OSC2 OSC1 OSC0 - PR2 Bit 1 Bit 0 PR1 PR0 Bits 10~9 (LVR1 ~ LVR0): Low Voltage Reset enable bits. If Vdd has crossover at Vdd reset level as Vdd changes, the system will reset.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM Bits 12 ~ 11 (Type 1, Type 0): Type selection for EM78P221N or EM78P222N Type 1, Type 0 MCU Type 00 01 10 11 Not for use Not for use EM78P221N (24 pins) EM78P222N (28 pins) Note: LVR1 and LVR0 are at Bank 3-R7, when using ICE. Bits 10 ~ 9 (LVR1 ~ LVR0): Low Voltage Reset control bits LVR1, LVR0 VDD Reset Level 11 10 01 00 VDD Release Level NA (Power-on Reset) (Default) 2.5V 2.7V 3.0V 3.2V 4.0V 4.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 6.11.2 Code Option Register (Word 1) Word 1 Bit 12 Bit 11 - - Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 RESET RCOUT NRHL NRE ENB - Bit 5 Bit 4 Bit 3 C3 C2 C1 Bit 2 Bit 1 C0 Bit 0 RCM1 RCM0 Bit 12: Not used (reserved), fixed to “1” all the time. Bit 11: Not used (reserved), fixed to “0” all the time.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM Bit 1 & Bit 0 (RCM1 & RCM0): RC mode selection bits RCM 1 RCM 0 Frequency (MHz) 1 1 4 (Default) 1 0 16 0 1 1 0 0 455kHz 6.11.3 Customer ID Register (Word 2) Word 2 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 - NRM - - ID8 Bit 7 ID7 Bit 6 Bit 5 ID6 ID5 Bit 4 Bit 3 Bit 2 ID4 ID3 ID2 Bit 1 Bit 0 ID1 ID0 Bit 12: Not used (reserved), fixed to “0” all the time Bit 11 (NRM): 0 = Noise reject Mode 2.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM HEX Mnemonic 0 0000 0000 0000 0000 NOP No Operation 0 0000 0000 0001 0001 DAA Decimal Adjust A 0 0000 0000 0010 0002 CONTW A → CONT None 0 0000 0000 0011 0003 SLEP 0 → WDT, Stop oscillator T, P 0 0000 0000 0100 0004 WDTC 0 → WDT T, P 0 0000 0001 0000 0010 ENI Enable Interrupt None 0 0000 0001 0001 0011 DISI Disable Interrupt None 0 0000 0001 0010 0012 RET [Top of Stack] → PC None 0 0000 0001 0011 0013 RETI [Top of Sta
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EM78P221/2N 8-Bit Microcontroller with OTP ROM Binary Instruction Operation Status Affected HEX Mnemonic 0 0101 01rr rrrr 05rr INC R R+1 → R 0 0101 10rr rrrr 05rr DJZA R R-1 → A, skip if zero None 0 0101 11rr rrrr 05rr DJZ R R-1 → R, skip if zero None 0 0110 00rr rrrr 06rr RRCA R R(n) → A(n-1), R(0) → C, C → A(7) C 0 0110 01rr rrrr 06rr RRC R R(n) → R(n-1), R(0) → C, C → R(7) C 0 0110 10rr rrrr 06rr RLCA R R(n) → A(n+1), R(7) → C, C → A(0) C 0 0110 11rr rrrr 06rr RLC R
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 7 Absolute Maximum Ratings Items 8 Rating Temperature under bias -40°C to 85°C Storage temperature -65°C to 150°C Input voltage Vss-0.3V to Vdd+0.5V Output voltage Vss-0.3V to Vdd+0.5V Working Voltage 2.3V to 5.5V Working Frequency DC to 16MHz DC Electrical Characteristics Ta= 25°C, VDD= 5.0V, VSS= 0V Symbol FXT Parameter Crystal: VDD to 5V Two cycles with two clocks ERC: VDD to 5V R: 5.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM Symbol IPH IPL Parameter Pull-high current (Ports 50~53, 64~67) Pull-low current (Ports 60~67) ISB1 Power down current ISB2 Power down current ISB3 Power down current ICC1 Operating supply current at two clocks (VDD=3V) ICC2 Operating supply current at two clocks (VDD=3V) ICC3 Operating supply current at two clocks (VDD=5V) ICC4 Operating supply current at two clocks (VDD=5V) Condition Min. Typ. Max.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 8.1 Comparator (OP) Characteristic Vdd = 5.0V, Vss=0V, Ta=25°C Symbol Parameter Condition 1 Min. Typ. Max. Unit − − 10 mV GND − VDD-1 V − 50 nA VOS Input Offset Voltage RL = 5.1K Note Vcm Input Common-Mode Voltage Range Note 2 IOS Input Offset Current − − IBS Input Bias Current − − 25 250 nA ICO Supply Current of Comparator − − 300 − μA TRS Response Time VREF=1.4V,VRL = 5V, RL = 5.1k, CL=15p, Note 3 0.5 1.3 3.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM 10 Timing Diagrams AC Test Input/Output Waveform VDD-0.5V 0.75VDD 0.75VDD 0.25VDD 0.25VDD TEST POINTS GND+0.5V AC Testing : Input is driven at VDD-0.5V for logic "1",and GND+0.5V for logic "0".Timing measurements are made at 0.75VDD for logic "1",and 0.25VDD for logic "0". RESET Timing (CLK="0") NOP Instruction 1 Executed CLK /RESET Tdrh TCC Input Timing (CLKS="0") Tins CLK TCC Ttcc 56 • Product Specification (V1.0) 10.19.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM APPENDIX A Package Type OTP MCU Package Type Pin Count Package Size EM78P221NKS/NKJ Skinny DIP 24 pins 300mil EM78P221NMS/NMJ SOP 24 pins 300mil SSOP 24 pins 209mil EM78P222NKS/NKJ Skinny DIP 28 pins 300mil EM78P222NMS/NMJ SOP 28 pins 300mil SSOP 28 pins 209mil EM78P221NAMS/NAMJ EM78P222NAMS/NAMJ Green products do not contain hazardous substances. The third edition of Sony SS-00259 standard.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM B Packaging Configuration B.1 24-Lead Plastic Skinny Dual in line (SDIP) — 300 mil 13 24 E 12 1 Symbal A A1 A2 c D E1 E eB B B1 L e Min 0.381 3.175 0.203 Normal Max 5.334 3.302 0.254 3.429 0.356 31.750 6.426 7.370 8.380 0.356 31.801 31.852 6.628 6.830 7.620 7.870 8.950 9.520 0.457 0.559 1.520 1.470 1.630 3.302 3.556 3.048 2.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM B.2 24-Lead Plastic Small Outline (SOP) — 300 mil Symbal A A1 b c E H D L e θ b Min Normal 2.350 0.102 Max 2.650 0.300 0.406(TYP) 0.230 7.400 10.000 15.200 0.630 0 0.838 1.27(TYP) 0.320 7.600 10.650 15.600 1.100 8 e c TITLE: SOP-24L(300MIL) PACKAGE OUTLINE DIMENSION File : Edtion: A SO24 Unit : mm Scale: Free Material: Sheet:1 of 1 Product Specification (V1.0) 10.19.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM B.3 24-Lead Plastic Shrink Small Outline (SSOP) — 209 mil 24 Symbal A A1 A2 b c D E E1 e L L1 13 1 12 θ Min 0.05 1.65 0.22 0.09 7.90 7.400 5.00 0.55 0° Normal - Max 1.75 - 1.85 0.38 8.20 7.80 5.30 0.65 0.75 1.25 - 2.00 - 0.25 8.50 8.200 5.60 0.95 8° A2 D TITLE: SSOP-24L(209MIL) PACKAGE OUTLINE DIMENSION File : SSO24 Edtion: A Unit : mm Scale: Free Material: Sheet:1 of 1 60 • Product Specification (V1.0) 10.19.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM B.4 28- Lead Plastic Skinny Dual in line (SDIP) — 300 mil Symbal A A1 A2 c D E1 E eB B B1 L e 0.381 3.175 0.152 35.204 7.213 7.620 8.382 0.356 1.422 3.251 0 Normal Max 5.334 3.302 0.254 3.429 0.356 35.255 35.306 7.315 7.417 7.874 8.128 8.890 9.398 0.457 0.559 1.524 1.626 3.302 3.353 2.540(TYP) 10 A θ Min TITLE: PDIP-28L SKINNY 300MIL PACKAGE OUTLINE DIMENSION File : Edtion: A K28 Unit : mm Scale: Free Material: Sheet:1 of 1 Product Specification (V1.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM B.5 28-Lead Plastic Small Outline (SOP) — 300 mil Symbal A A1 b c E E1 D L L1 e θ Min Normal Max 2.370 0.102 0.350 2.500 2.630 0.300 0.500 7.410 10.000 17.700 0.678 1.194 0 0.406 0.254(TYP) 7.500 10.325 17.900 0.881 1.397 1.27(TYP) 7.590 10.650 18.100 1.084 1.600 8 TITLE: SOP-28L(300MIL) PACKAGE OUTLINE DIMENSION File : Edtion: A SO28 Unit : mm Scale: Free Material: Sheet:1 of 1 62 • Product Specification (V1.0) 10.19.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM Symbal A A1 A2 b c E E1 D L e E E1 B.6 28- Lead Plastic Shrink Small Outline (SSOP) — 209 mil θ b Min Normal 0.050 1.620 0.220 0.090 1.750 7.400 5.000 9.900 0.630 7.800 5.300 10.200 0.900 0.650(TYP) 0 4 Max 2.130 0.250 1.880 0.380 0.200 8.200 5.600 10.500 1.030 8 e A2 c TITLE: SSOP-28L(209MIL) OUTLINE PACKAGE PACKA OUTLINE DIMENSION File : Edtion: A SSO28 Unit : mm Scale: Free Material: Sheet:1 of 1 Product Specification (V1.0) 10.19.
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EM78P221/2N 8-Bit Microcontroller with OTP ROM C Quality Assurance and Reliability Test Category Test Conditions Remarks Solder temperature=245±5°C, for 5 seconds up to the stopper using a rosin-type flux Solderability − Step 1: TCT, 65°C (15 mins)~150°C (15 mins), 10 cycles Step 2: Bake at 125°C, TD (endurance)=24 hrs Step 3: Soak at 30°C/60% , TD (endurance)=192 hrs For SMD IC (such as SOP, QFP, SOJ, etc) Pre-condition Step 4: IR flow 3 cycles (Pkg thickness: 2.