User Manual
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1 55
Electrical Specifications
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All AC timings for the Asynchronous GTL signals are referenced to the BCLK_P rising edge at Crossing
Voltage (V
CROSS
). VCCPWRGOOD, VTTPWRGOOD and VDDPWRGOOD are referenced to BCLK_P rising edge
at 0.5 * V
TT
.
3. These signals may be driven asynchronously.
4. Refer to Section 8 for additional timing requirements for entering and leaving low power states.
5. xxPWRGOOD signal has no edge rate requirement, but edge must be monotonic.
6. VDDPWRGOOD must be asserted no later then VCCPWRGOOD. There is no releationship between
VDDPWRGOOD and VCC ramp.
7. There is no dependency between VDDPWRGOOD and VTTPWRGOOD assertion.
8. VTTPWRGOOD must accurately reflect the state of VTT and must not glitch whenever VTT or VDD is
applied.
9. VTT must read VTTFINAL before VCCPWRGOOD assertion.
10. It may be required to add delay on the board to meet the 1 ms minimum processor requirement.
11. Based on a test load of 50 to V
TT
.
12. Specified for synchronous signals.
13. Applies to PROCHOT# signal only. Please see Section 2.1.7.3.1 and Section 8.1 for information regarding
Power-On Configuration options.
14. Rise time is measured from 10% to 90% of the final voltage.
Table 2-26. Processor Sideband Signal Group AC Specifications
T# Parameter Min Max Unit Figure
Notes
1,2,3,4
Asynchronous GTL input pulse width 8 BCLKs
Tb: V
TT
stable to VTTPWRGOOD assertion 1 500 ms 2-28 5,7,8,10
Td: VTTPWRGOOD assertion to Dynamic V
TT
VID from
Processor
10 µs 2-28 9
Te: V
DDQ
stable to VDDPWRGOOD assertion 100 ns 2-28 5,6,7
Tf: VTTPWRGOOD to valid VID 0 10 µs 2-28
Th: V
CC
stable to VCCPWRGOOD assertion 0.05 650 ms 2-28
Ti: V
CCPLL
stable to VCCPWRGOOD assertion 1 ms 2-28
Tj: BCLK stable to VCCPWRGOOD assertion 10 BCLKs 2-28
Tk: VCCPWRGOOD assertion to RESET# de-assertion 1 10 ms 2-28
Tm: VTTPWRGOOD assertion to VCCPWRGOOD
assertion
1ms2-28
Tn: V
CCPLL
rise time 1.5 ms 2-28 14
Tq: PROCHOT# pulse width 500 µs 2-26
Tr:THERMTRIP# assertion until V
CC
/ V
TT
removed 500 ms 2-27
VTTPWRGOOD de-assertion to V
TT
below specification 100 ns
T
CO
: Time from BCLK land until signal valid at output 0.5 2.275 ns 11
T
SU
: Processor Sideband Input signals with respect to
BCLK
600 ps 12
T
H
: Processor Sideband Input signals with respect to
BCLK
600 ps
T
H
: Power-On Configuration Hold Time (PROCHOT#) 106 BCLK 8-1 13