User Manual

Electrical Specifications
44 Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
Note:
1. V
TTD
supplies the PECI interface. PECI behavior does not affect V
TTD
min/max specifications.
2. It is expected that the PECI driver will take into account, the variance in the receiver input thresholds and
consequently, be able to drive its output within safe limits (-0.150 V to 0.275*V
TTD
for the low level and
0.725*V
TTD
to V
TTD
+0.150 for the high level).
3. The leakage specification applies to powered devices on the PECI bus.
4. One node is counted for each client and one node for the system host. Extended trace lengths might appear
as additional nodes.
5. Excessive capacitive loading on the PECI line may slow down the signal rise/fall times and consequently
limit the maximum bit rate at which the interface can operate.
6. Please refer to Figure 2-2 for further information.
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK_DN is equal to
the falling edge of BCLK_DP.
3. V
Havg
is the statistical average of the VH measured by the oscilloscope.
4. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
5. V
Havg
can be measured directly using “Vtop” on Agilent* and “High” on Tektronix* oscilloscopes.
6. V
CROSS
is defined as the total variation of all crossing voltages as defined in Note 2.
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The V
TTA
referred to in these specifications refers to instantaneous V
TTA
.
3. For V
IN
between 0 V and V
TTA
. Measured when the driver is tri-stated.
4. V
IH
may experience excursions above V
TT
. However, input signal drivers must comply with the signal quality
specifications in Section 3.
I
Leak-
High impedance leakage to GND
(V
leak
= V
OH
)
N/A 25 µA 3
C
Bus
Bus capacitance per node N/A 10 pF 4,5
V
Noise
Signal noise immunity above
300 MHz
0.100 * V
TTD
N/A V
p-p
Table 2-13. PECI Signal DC Electrical Limits (Sheet 2 of 2)
Symbol Definition and Conditions Min Max Units Notes
1
Table 2-14. System Reference Clock DC Specifications
Symbol Parameter Min Max
Unit Figure Notes
1
V
BCLK_diff_ih
Differential Input High
Voltage
0.150 N/A V
V
BCLK_diff_il
Differential Input Low
Voltage
N/A -0.150 V
V
cross
(abs)
Absolute
Crossing Point
0.250 0.550 V
2-16
2-19
2, 4
V
cross
(rel)
Relative
Crossing Point
0.250 +
0.5*(VH
avg
- 0.700)
0.550 +
0.5*(VH
avg
- 0.700)
V 2-16 3,4,5
V
cross
Range of
Crossing Points
N/A 0.140 V 2-20 6
Table 2-15. RESET# Signal DC Specifications
Symbol Parameter Min Typ Max Units Notes
1
V
IL
Input Low Voltage
0.6 * V
TTA
V2
V
IH
Input High Voltage
0.7 * V
TTA
V2,4
R
ON
Buffer On Resistance
10 18

I
LI
Input Leakage Current ± 200 A
3