User Manual

Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1 29
Electrical Specifications
Signals that include on-die termination (ODT) are listed in Table 2-6.
Notes:
1. Unless otherwise specified, signals have ODT in the package with a 50  pull-down to V
SS
.
2. Unless otherwise specified, all DDR3 signals are terminated to V
DDQ
/2.
3. DDR{0/1/2}_PAR_ERR#[2:0] are terminated to V
DDQ.
4. TCK does not include ODT, this signal is weakly pulled-down via a 1-5 k resistor to V
SS
.
5. TDI, TMS, TRST# do not include ODT, these signals are weakly pulled-up via 1-5k resistor to V
TT
.
6. BPM[7:0]# and PREQ# signals have ODT in package with 35 pull-ups to V
TT.
7. PECI_ID# has ODT in package with a 1-5 kpull-up to V
TT
.
8. TAPPWRGOOD has ODT in package with a 1-2.5 kpull-up to V
TT
.
9. VCCPWRGOOD, VDDPWRGOOD, and VTTPWRGOOD have ODT in package with a 5-20 kpull-down to V
SS
.
2.3 Mixing Processors
Intel supports dual-processor (DP) configurations consisting of processors:
• from the same power optimization segment.
• that support the same maximum Intel
®
QuickPath Interconnect and DDR3 memory
speeds.
System Reference Clock
Differential Input BCLK_DP, BCLK_DN
Test Access Port (TAP) Signals
Differential CMOS Output BCLK_ITP_DP, BCLK_ITP_DN
Single ended Input TCK, TDI, TMS, TRST#
Single ended GTL Output TDO
Power/Other Signals
Power / Ground V
CC
, V
CCPLL
, V
DDQ
, V
TTA
, V
TTD
, V
SS
Analog Input COMP0, ISENSE
Sense Points VCCSENSE, VSSSENSE, VSS_SENSE_VTTD,
VTTD_SENSE
Other SKTOCC#, DBR#
Notes:
1. Refer to Section 5 for land assignments and Section 6 for signal definitions.
2. DDR{0/1/2} refers to DDR3 channel 0, DDR3 channel 1, and DDR3 Channel 2
Table 2-5. Signal Groups (Sheet 2 of 2)
Signal Group Buffer Type Signals
1
Table 2-6. Signals With On-Die Termination (ODT)
Intel QuickPath Interface Signal Group
1
QPI[1:0]_DRX_DP[19:0], QPI[1:0]_DRX_DN[19:0], QPI[1:0]_TRX_DP[19:0], QPI[1:0]_TRX_DN[19:0],
QPI[0/1]_CLKRX_D[N/P], QPI[0/1]_CLKTX_D[N/P]
DDR3 Signal Group
1,2
DDR{0/1/2}_DQ[63:0], DDR{0/1/2}_DQS_[N/P][17:0], DDR{0/1/2}_ECC[7:0],
DDR{0/1/2}_PAR_ERR#[2:0]
3
Processor Sideband Signal Group
1
BPM#[7:0]
6
, PECI_ID#
7
, PREQ#
6,
TAPPWRGOOD
8
Test Access Port (TAP) Signal Group
TCK
4
, TDI
5
, TMS
5
, TRST#
5
Power/Other Signal Group
9
TAPPWRGOOD
8
, VCCPWRGOOD, VDDPWRGOOD, VTTPWRGOOD