User Manual

Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1 141
Thermal Specifications
Note:
1. Currently not available for access through the PECI PCIConfigWr() command.
PCI configuration addresses are constructed as shown in Figure 7-20, and this
command is subject to the same address configuration rules as defined in
Section 7.3.2.4. PCI configuration reads may be issued in byte, word, or dword
granularities.
Because a PCIConfigWr() results in an update to potentially critical registers inside the
processor, it includes an Assured Write FCS (AW FCS) byte as part of the write data
payload. In the event that the AW FCS mismatches with the client-calculated FCS, the
client will abort the write and will always respond with a bad Write FCS.
7.3.2.5.1 Command Format
The PCIConfigWr() format is as follows:
Write Length: 7 (byte), 8 (word), 10 (dword)
Read Length: 1
Command: 0xc5
Multi-Domain Support: Yes (see Table 7-32)
Description: Writes the data sent to the requested register address. Write Length
dictates the desired write granularity. The command always returns a completion code
indicating the pass/fail status information. Write commands issued to illegal (non-zero)
Bus Numbers, or unimplemented Device / Function / Register addresses are ignored
but return a passing completion code. Refer to Section 7.3.4.2 for details regarding
completion codes.
4 3 Memory Controller Channel 0 Thermal Control / Status
5 3 Memory Controller Channel 1 Thermal Control / Status
6 3 Memory Controller Channel 2 Thermal Control / Status
Table 7-23. PCIConfigWr() Device/Function Support (Sheet 2 of 2)
Writable
Description
Device Function