Datasheet
Table Of Contents
- Description
- Features
- Ordering Information
- Key Parameters
- Speed Grade
- Address Table
- Pin Descriptions
- Input/Output Functional Descriptions
- Pin Assignments
- Registering Clock Driver Specifications
- On DIMM Thermal Sensor
- Functional Block Diagram
- 4GB, 512Mx72 Module(1Rank of x8)
- 8GB, 1Gx72 Module(1Rank of x4) - page1
- 8GB, 1Gx72 Module(1Rank of x4) - page2
- 8GB, 1Gx72 Module(2Rank of x8) - page1
- 8GB, 1Gx72(2Rank of x8) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page1
- 16GB, 2Gx72 Module(2Rank of x4) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page1
- 32GB, 4Gx72 Module(4Rank of x4) - page2
- 32GB, 4Gx72 Module(4Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page4
- 32GB, 4Gx72 Module(4Rank of x4) - page5
- Absolute Maximum Ratings
- AC & DC Operating Conditions
- AC & DC Input Measurement Levels
- Vref Tolerances
- AC and DC Logic Input Levels for Differential Signals
- Differential signal definition
- Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
- note : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VIL(ac) level.
- Single-ended requirements for differential signals
- Differential Input Cross Point Voltage
- Slew Rate Definitions for Single-Ended Input Signals
- Slew Rate Definitions for Differential Input Signals
- AC & DC Output Measurement Levels
- Overshoot and Undershoot Specifications
- Refresh parameters by device density
- Standard Speed Bins
- Environmental Parameters
- IDD and IDDQ Specification Parameters and Test Conditions
- IDD Specifications (Tcase: 0 to 95oC)
- Module Dimensions
Rev. 1.0 / May. 2014 8
Pin Assignments
Pin #
Front Side
(left 1–60)
Pin #
Back Side
(right 121–180)
Pin #
Front Side
(left 61–120)
Pin #
Back Side
(right 181–240)
1VREFDQ 121
V
SS
61 A2 181 A1
2
V
SS
122 DQ4 62 VDD 182 VDD
3 DQ0 123 DQ5 63 NC, CK1 183 VDD
4 DQ1 124
V
SS
64 NC, CK1 184 CK0
5
V
SS
125
DM0,DQS9,
TDQS9
65 VDD 185 CK0
6DQS0126
NC,DQS9
,
TDQS9
66 VDD 186 VDD
7 DQS0 127
V
SS
67 VREFCA 187 EVENT, NC
8
V
SS
128 DQ6 68 Par_In, NC 188 A0
9 DQ2 129 DQ7 69 VDD 189 VDD
10 DQ3 130
V
SS
70 A10 / AP 190 BA1
11
V
SS
131 DQ12 71 BA0 191 VDD
12 DQ8 132 DQ13 72 VDD 192 RAS
13 DQ9 133
V
SS
73 WE 193 S0
14
V
SS
134
DM1,DQS10,
TDQS10
74 CAS 194 VDD
15 DQS1 135
NC,DQS10
,
TDQS10
75 VDD 195 ODT0
16 DQS1 136
V
SS
76 S1, NC 196 A13
17
V
SS
137 DQ14 77 ODT1, NC 197 VDD
18 DQ10 138 DQ15 78 VDD 198 S3, NC
19 DQ11 139
V
SS
79 S2, NC 199
V
SS
20
V
SS
140 DQ20 80
V
SS
200 DQ36
21 DQ16 141 DQ21 81 DQ32 201 DQ37
22 DQ17 142
V
SS
82 DQ33 202
V
SS
23
V
SS
143
DM2,DQS11,
TDQS11
83
V
SS
203
DM4,DQS13,
TDQS13
24 DQS2
144
NC,DQS11
,
TDQS11
84 DQS4 204
NC,DQS13
,
TDQS13
25 DQS2 145
V
SS
85 DQS4 205
V
SS
26
V
SS
146 DQ22 86
V
SS
206 DQ38
27 DQ18 147 DQ23 87 DQ34 207 DQ39
28 DQ19 148
V
SS
88 DQ35 208
V
SS
29
V
SS
149 DQ28 89
V
SS
209 DQ44
30 DQ24 150 DQ29 90 DQ40 210 DQ45
31 DQ25 151
V
SS
91 DQ41 211
V
SS
NC = No Connect; RFU = Reserved Future Use