Datasheet
Table Of Contents
- Description
- Features
- Ordering Information
- Key Parameters
- Speed Grade
- Address Table
- Pin Descriptions
- Input/Output Functional Descriptions
- Pin Assignments
- Registering Clock Driver Specifications
- On DIMM Thermal Sensor
- Functional Block Diagram
- 4GB, 512Mx72 Module(1Rank of x8)
- 8GB, 1Gx72 Module(1Rank of x4) - page1
- 8GB, 1Gx72 Module(1Rank of x4) - page2
- 8GB, 1Gx72 Module(2Rank of x8) - page1
- 8GB, 1Gx72(2Rank of x8) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page1
- 16GB, 2Gx72 Module(2Rank of x4) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page1
- 32GB, 4Gx72 Module(4Rank of x4) - page2
- 32GB, 4Gx72 Module(4Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page4
- 32GB, 4Gx72 Module(4Rank of x4) - page5
- Absolute Maximum Ratings
- AC & DC Operating Conditions
- AC & DC Input Measurement Levels
- Vref Tolerances
- AC and DC Logic Input Levels for Differential Signals
- Differential signal definition
- Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
- note : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VIL(ac) level.
- Single-ended requirements for differential signals
- Differential Input Cross Point Voltage
- Slew Rate Definitions for Single-Ended Input Signals
- Slew Rate Definitions for Differential Input Signals
- AC & DC Output Measurement Levels
- Overshoot and Undershoot Specifications
- Refresh parameters by device density
- Standard Speed Bins
- Environmental Parameters
- IDD and IDDQ Specification Parameters and Test Conditions
- IDD Specifications (Tcase: 0 to 95oC)
- Module Dimensions
Rev. 1.0 / May. 2014 7
DQS[17:0] I/O
Positive
Edge
Positive line of the differential data strobe for input and output data.
DQS[17:0]
I/O
Negative
Edge
Negative line of the differential data strobe for input and output data.
TDQS[17:9]
TDQS[17:9]
OUT
TDQS/TDQS
is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in
MR1,DRAM will enable the same termination resistance function on TDQS/TDQS
that is
applied to DQS/DQS
. When disabled via mode register A11=0 in MR1, DM/TDQS will
provide the data mask function and TDQS
is not used. X4/X16 DRAMs must disable the
TDQS function via mode register A11=0 in MR1
SA[2:0] IN —
These signals are tied at the system planar to either V
SS
or V
DDSPD
to configure the
serial SPD EEPROM address range.
SDA I/O —
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DDSPD
on the system planar to act as a
pullup.
SCL IN —
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected from the SCL bus time to V
DDSPD
on the system planar to act as a pullup.
EVENT
OUT
(open
drain)
Active Low
This signal indicates that a thermal event has been detected in the thermal sensing
device.The system should guarantee the electrical level requirement is met for the
EVENT
pin on TS/SPD part.
No pull-up resister is provided on DIMM.
V
DDSPD
Supply
Serial EEPROM positive power supply wired to a separate power pin at the connector
which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
RESET
IN
The RESET
pin is connected to the RESET pin on the register and to the RESET pin on
the DRAM.
Par_In IN Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even)
Err_Out
OUT
(open
drain)
Parity error detected on the Address and Control bus. A resistor may be connected from
Err_Out
bus line to V
DD
on the system planar to act as a pull up.
TEST Used by memory bus analysis tools (unused (NC) on memory DIMMs)
Symbol Type Polarity Function