Datasheet
Table Of Contents
- Description
- Features
- Ordering Information
- Key Parameters
- Speed Grade
- Address Table
- Pin Descriptions
- Input/Output Functional Descriptions
- Pin Assignments
- Registering Clock Driver Specifications
- On DIMM Thermal Sensor
- Functional Block Diagram
- 4GB, 512Mx72 Module(1Rank of x8)
- 8GB, 1Gx72 Module(1Rank of x4) - page1
- 8GB, 1Gx72 Module(1Rank of x4) - page2
- 8GB, 1Gx72 Module(2Rank of x8) - page1
- 8GB, 1Gx72(2Rank of x8) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page1
- 16GB, 2Gx72 Module(2Rank of x4) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page1
- 32GB, 4Gx72 Module(4Rank of x4) - page2
- 32GB, 4Gx72 Module(4Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page4
- 32GB, 4Gx72 Module(4Rank of x4) - page5
- Absolute Maximum Ratings
- AC & DC Operating Conditions
- AC & DC Input Measurement Levels
- Vref Tolerances
- AC and DC Logic Input Levels for Differential Signals
- Differential signal definition
- Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
- note : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VIL(ac) level.
- Single-ended requirements for differential signals
- Differential Input Cross Point Voltage
- Slew Rate Definitions for Single-Ended Input Signals
- Slew Rate Definitions for Differential Input Signals
- AC & DC Output Measurement Levels
- Overshoot and Undershoot Specifications
- Refresh parameters by device density
- Standard Speed Bins
- Environmental Parameters
- IDD and IDDQ Specification Parameters and Test Conditions
- IDD Specifications (Tcase: 0 to 95oC)
- Module Dimensions
Rev. 1.0 / May. 2014 60
Table 9 - IDD5B Measurement-Loop Pattern
a)
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data
b)
toggling
Static High
0
0
REF 0 0 0 1 0 0 0 0 0 0 0 -
11.2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D
, D 111100000 0 F0 -
5...8 repeat cycles 1...4, but BA[2:0] = 1
9...12 repeat cycles 1...4, but BA[2:0] = 2
13...16 repeat cycles 1...4, but BA[2:0] = 3
17...20 repeat cycles 1...4, but BA[2:0] = 4
21...24 repeat cycles 1...4, but BA[2:0] = 5
25...28 repeat cycles 1...4, but BA[2:0] = 6
29...32 repeat cycles 1...4, but BA[2:0] = 7
2 33...nRFC-1 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.