Datasheet
Table Of Contents
- Description
- Features
- Ordering Information
- Key Parameters
- Speed Grade
- Address Table
- Pin Descriptions
- Input/Output Functional Descriptions
- Pin Assignments
- Registering Clock Driver Specifications
- On DIMM Thermal Sensor
- Functional Block Diagram
- 4GB, 512Mx72 Module(1Rank of x8)
- 8GB, 1Gx72 Module(1Rank of x4) - page1
- 8GB, 1Gx72 Module(1Rank of x4) - page2
- 8GB, 1Gx72 Module(2Rank of x8) - page1
- 8GB, 1Gx72(2Rank of x8) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page1
- 16GB, 2Gx72 Module(2Rank of x4) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page1
- 32GB, 4Gx72 Module(4Rank of x4) - page2
- 32GB, 4Gx72 Module(4Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page4
- 32GB, 4Gx72 Module(4Rank of x4) - page5
- Absolute Maximum Ratings
- AC & DC Operating Conditions
- AC & DC Input Measurement Levels
- Vref Tolerances
- AC and DC Logic Input Levels for Differential Signals
- Differential signal definition
- Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
- note : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VIL(ac) level.
- Single-ended requirements for differential signals
- Differential Input Cross Point Voltage
- Slew Rate Definitions for Single-Ended Input Signals
- Slew Rate Definitions for Differential Input Signals
- AC & DC Output Measurement Levels
- Overshoot and Undershoot Specifications
- Refresh parameters by device density
- Standard Speed Bins
- Environmental Parameters
- IDD and IDDQ Specification Parameters and Test Conditions
- IDD Specifications (Tcase: 0 to 95oC)
- Module Dimensions
Rev. 1.0 / May. 2014 4
Key Parameters
*SK hynix DRAM devices support optional downbinning to CL11, CL9 and CL7. SPD setting is programmed to match.
Speed Grade
Address Table
MT/s Grade
tCK
(ns)
CAS
Latency
(tCK)
tRCD
(ns)
tRP
(ns)
tRAS
(ns)
tRC
(ns)
CL-tRCD-tRP
DDR3-1066 -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7
DDR3-1333 -H9 1.5 9
13.5
(13.125)*
13.5
(13.125)*
36
49.5
(49.125)*
9-9-9
DDR3-1600 -PB 1.25 11
13.75
(13.125)*
13.75
(13.125)*
35
48.75
(48.125)*
11-11-11
DDR3-1866 -Rd 1.07 13
13.91
(13.125)*
13.91
(13.125)*
34
47.91
(48.125)*
13-13-13
Grade
Frequency [MHz]
Remark
CL6 CL7 CL8 CL9 CL10 CL11 CL12 CL13
-G7 800 1066 1066
-H9 800 1066 1066 1333 1333
-PB 800 1066 1066 1333 1333 1600
-RD 800 1066 1066 1333 1333 1600 1866
4GB(1Rx8) 8GB(1Rx4) 8GB(2Rx8) 16GB(2Rx4) 32GB(4Rx4)
Refresh Method 8K/64ms 8K/64ms 8K/64ms 8K/64ms 8K/64ms
Row Address A0-A15 A0-A15 A0-A15 A0-A15 A0-A15
Column Address A0-A9 A0-A9,A11 A0-A9 A0-A9,A11 A0-A9,A11
Bank Address BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2
Page Size 1KB 1KB 1KB 1KB 1KB