Datasheet
Table Of Contents
- Description
- Features
- Ordering Information
- Key Parameters
- Speed Grade
- Address Table
- Pin Descriptions
- Input/Output Functional Descriptions
- Pin Assignments
- Registering Clock Driver Specifications
- On DIMM Thermal Sensor
- Functional Block Diagram
- 4GB, 512Mx72 Module(1Rank of x8)
- 8GB, 1Gx72 Module(1Rank of x4) - page1
- 8GB, 1Gx72 Module(1Rank of x4) - page2
- 8GB, 1Gx72 Module(2Rank of x8) - page1
- 8GB, 1Gx72(2Rank of x8) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page1
- 16GB, 2Gx72 Module(2Rank of x4) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page1
- 32GB, 4Gx72 Module(4Rank of x4) - page2
- 32GB, 4Gx72 Module(4Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page4
- 32GB, 4Gx72 Module(4Rank of x4) - page5
- Absolute Maximum Ratings
- AC & DC Operating Conditions
- AC & DC Input Measurement Levels
- Vref Tolerances
- AC and DC Logic Input Levels for Differential Signals
- Differential signal definition
- Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
- note : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VIL(ac) level.
- Single-ended requirements for differential signals
- Differential Input Cross Point Voltage
- Slew Rate Definitions for Single-Ended Input Signals
- Slew Rate Definitions for Differential Input Signals
- AC & DC Output Measurement Levels
- Overshoot and Undershoot Specifications
- Refresh parameters by device density
- Standard Speed Bins
- Environmental Parameters
- IDD and IDDQ Specification Parameters and Test Conditions
- IDD Specifications (Tcase: 0 to 95oC)
- Module Dimensions
Rev. 1.0 / May. 2014 29
Vref Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages
VRefCA
and V
RefDQ
are illustrated in
figure below. It shows a valid reference voltage V
Ref
(t) as a function of time. (V
Ref
stands for V
RefCA
and
V
RefDQ
likewise).
V
Ref
(DC) is the linear average of V
Ref
(t) over a very long period of time (e.g. 1 sec). This average has to
meet the min/max requirements in the table "Differential Input Slew Rate Definition" on page 35. Further-
more V
Ref
(t) may temporarily deviate from V
Ref (DC)
by no more than +/- 1% VDD.
Illustration of V
Ref(DC)
tolerance and V
Ref
ac-noise limits
The voltage levels for setup and hold time measurements V
IH(AC)
, V
IH(DC)
, V
IL(AC)
, and V
IL(DC)
are depen-
dent on V
Ref
.
“V
Ref
” shall be understood as V
Ref(DC)
, as defined in figure above.
This clarifies that dc-variations of V
Ref
affect the absolute voltage a signal has to reach to achieve a valid
high or low level and therefore the time to which setup and hold is measured. System timing and voltage
budgets need to account for V
Ref(DC)
deviations from the optimum position within the data-eye of the input
signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and
voltage associated with V
Ref
ac-noise. Timing and voltage effects due to ac-noise on V
Ref
up to the speci-
fied limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.
VDD
VSS
VDD/2
V
Ref(DC)
V
Ref
ac-noise
voltage
time
V
Ref(DC)max
V
Ref(DC)min
V
Ref
(t)