Datasheet
Table Of Contents
- Description
- Features
- Ordering Information
- Key Parameters
- Speed Grade
- Address Table
- Pin Descriptions
- Input/Output Functional Descriptions
- Pin Assignments
- Registering Clock Driver Specifications
- On DIMM Thermal Sensor
- Functional Block Diagram
- 4GB, 512Mx72 Module(1Rank of x8)
- 8GB, 1Gx72 Module(1Rank of x4) - page1
- 8GB, 1Gx72 Module(1Rank of x4) - page2
- 8GB, 1Gx72 Module(2Rank of x8) - page1
- 8GB, 1Gx72(2Rank of x8) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page1
- 16GB, 2Gx72 Module(2Rank of x4) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page1
- 32GB, 4Gx72 Module(4Rank of x4) - page2
- 32GB, 4Gx72 Module(4Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page4
- 32GB, 4Gx72 Module(4Rank of x4) - page5
- Absolute Maximum Ratings
- AC & DC Operating Conditions
- AC & DC Input Measurement Levels
- Vref Tolerances
- AC and DC Logic Input Levels for Differential Signals
- Differential signal definition
- Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
- note : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VIL(ac) level.
- Single-ended requirements for differential signals
- Differential Input Cross Point Voltage
- Slew Rate Definitions for Single-Ended Input Signals
- Slew Rate Definitions for Differential Input Signals
- AC & DC Output Measurement Levels
- Overshoot and Undershoot Specifications
- Refresh parameters by device density
- Standard Speed Bins
- Environmental Parameters
- IDD and IDDQ Specification Parameters and Test Conditions
- IDD Specifications (Tcase: 0 to 95oC)
- Module Dimensions
Rev. 1.0 / May. 2014 27
AC & DC Input Measurement Levels
AC and DC Logic Input Levels for Single-Ended Signals
AC and DC Input Levels for Single-Ended Command and Address Signals
Notes:
1. For input only pins except RESET, Vref = VrefCA (DC).
2. Refer to "Overshoot and Undershoot Specifications" on page 40.
3. The ac peak noise on V
Ref
may not allow V
Ref
to deviate from V
RefCA(DC)
by more than +/-1% VDD (for refer-
ence: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)
7. VIH(ac) is used as simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135), and VIH.CA(AC125);
VIH.CA(AC175) value is used when Vref + 0.175V is referenced, VIH.CA(AC150) value is used when Vref +
0.150V is referenced, VIH.CA(AC135) value is used when Vref + 0.135V is referenced, and VIH.CA(AC125) value
is used when Vref + 0.125V is referenced.
8. VIL(ac) is used as simplified symbol for VIL.CA(AC175), VIL.CA(AC150), VIL.CA(AC135), and VIL.CA(AC125);
VIL.CA(AC175) value is used when Vref - 0.175V is referenced, VIL.CA(AC150) value is used when Vref - 0.150V is
referenced, VIL.CA(AC135) value is used when Vref - 0.135V is referenced, and VIL.CA(AC125) value is used
when Vref - 0.125V is referenced.
Single Ended AC and DC Input Levels for Command and ADDress
Symbol Parameter
DDR3-800/1066/1333/1600 DDR3-1866
Unit Notes
Min Max Min Max
VIH.CA(DC100) DC input logic high Vref + 0.100 VDD Vref + 0.100 VDD V 1, 5
VIL.CA(DC100) DC input logic low VSS Vref - 0.100 VSS Vref - 0.100 V 1, 6
VIH.CA(AC175) AC input logic high Vref + 0.175 Note2 - - V 1, 2, 7
VIL.CA(AC175) AC input logic low Note2 Vref - 0.175 - - V 1, 2, 8
VIH.CA(AC150) AC Input logic high Vref + 0.150 Note2 - - V 1, 2, 7
VIL.CA(AC150) AC input logic low Note2 Vref - 0.150 - - V 1, 2, 8
VIH.CA(AC135) AC input logic high - - Vref + 0.135 Note2 V 1, 2, 7
VIL.CA(AC135) AC input logic low - - Note2 Vref - 0.135 V 1, 2, 8
VIH.CA(AC125) AC Input logic high - - Vref + 0.125 Note2 V 1, 2, 7
VIL.CA(AC125) AC input logic low - - Note2 Vref - 0.125 V 1, 2, 8
V
RefCA(DC
)
Reference Voltage for
ADD, CMD inputs
0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3, 4