Datasheet
Table Of Contents
- Description
- Features
- Ordering Information
- Key Parameters
- Speed Grade
- Address Table
- Pin Descriptions
- Input/Output Functional Descriptions
- Pin Assignments
- Registering Clock Driver Specifications
- On DIMM Thermal Sensor
- Functional Block Diagram
- 4GB, 512Mx72 Module(1Rank of x8)
- 8GB, 1Gx72 Module(1Rank of x4) - page1
- 8GB, 1Gx72 Module(1Rank of x4) - page2
- 8GB, 1Gx72 Module(2Rank of x8) - page1
- 8GB, 1Gx72(2Rank of x8) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page1
- 16GB, 2Gx72 Module(2Rank of x4) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page1
- 32GB, 4Gx72 Module(4Rank of x4) - page2
- 32GB, 4Gx72 Module(4Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page4
- 32GB, 4Gx72 Module(4Rank of x4) - page5
- Absolute Maximum Ratings
- AC & DC Operating Conditions
- AC & DC Input Measurement Levels
- Vref Tolerances
- AC and DC Logic Input Levels for Differential Signals
- Differential signal definition
- Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
- note : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VIL(ac) level.
- Single-ended requirements for differential signals
- Differential Input Cross Point Voltage
- Slew Rate Definitions for Single-Ended Input Signals
- Slew Rate Definitions for Differential Input Signals
- AC & DC Output Measurement Levels
- Overshoot and Undershoot Specifications
- Refresh parameters by device density
- Standard Speed Bins
- Environmental Parameters
- IDD and IDDQ Specification Parameters and Test Conditions
- IDD Specifications (Tcase: 0 to 95oC)
- Module Dimensions
Rev. 1.0 / May. 2014 23
32GB, 4Gx72 Module(4Rank of x4) - page4
ZQ
ARRASB
ARCASB
ARS0B
ARWEB
APCK0B
APCK0B
ARCKE0B
ARODT0B
ARA[N:O]B
Vtt
/ARBA[N:O]B
DQ[39:36]
DQS13
DQS13
DQS
DQS
DM
D29
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D28
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
D31
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D30
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D33
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D32
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D35
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D34
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
BRRASB
BRCASB
BRS2B
BRWEB
BPCK0B
BPCK0B
BRCKE0B
BRODT1B
BRA[N:O]B
/BRBA[N:O]B
DQS
DQS
DM
D61
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D60
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D59
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D58
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D57
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D56
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D55
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D54
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSSVSSVSSVSS
ARS1B
ARCKE1B
VDD
BRS3B
BRCKE1B
VDD
DQ[47:44]
DQS14
DQS14
DQS
DQS
DM
DQ [3:0]
ZQ
DQS
DQS
DM
DQ [3:0]
ZQ
VSS
DQS
DQS
DM
DQ [3:0]
ZQ
DQS
DQS
DM
DQ [3:0]
ZQVSSVSSVSSVSS
DQ[55:52]
DQS15
DQS15
DQS
DQS
DM
DQ [3:0]
DQS
DQS
DM
DQ [3:0]
ZQ
VSS
DQS
DQS
DM
DQ [3:0]
ZQ
DQS
DQS
DM
DQ [3:0]
ZQVSSVSSVSSVSS
DQ[63:60]
DQS16
DQS16
DQS
DQS
DM
DQ [3:0]
ZQ
DQS
DQS
DM
DQ [3:0]
ZQ
VSS
DQS
DQS
DM
DQ [3:0]
ZQ
DQS
DQS
DM
DQ [3:0]
ZQVSSVSSVSSVSS
ZQ
D0–D71
V
DD
V
TT
V
DDSPD
D0–D71
VREFDQ
SPD
VREFCA
V
SS
D0–D71
D0–D71
Note:
1. DQ-to-I/O wiring may be changed within a nibble.
2. Unless otherwise noted, resistor values are 15 Ohms ±5%.
3. See the wiring diagrams for all resistors associated with the command, address and
control bus.
4. ZQ resistors are 240 Ohms ±1%. For all other resistor values refer to the appropriate
wiring diagram.
VDDSPD
EVENT
SCL
SDA
SA0
SPD with
Integrated
TS
SA1
SA2
VSS
VDDSPD
EVENT
SCL
SDA
SA0
SA1
SA2
VSS
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s requests. For more
details of SPD and Thermal sensor, please contact
local Hynix sales representative