Datasheet
Table Of Contents
- Description
- Features
- Ordering Information
- Key Parameters
- Speed Grade
- Address Table
- Pin Descriptions
- Input/Output Functional Descriptions
- Pin Assignments
- Registering Clock Driver Specifications
- On DIMM Thermal Sensor
- Functional Block Diagram
- 4GB, 512Mx72 Module(1Rank of x8)
- 8GB, 1Gx72 Module(1Rank of x4) - page1
- 8GB, 1Gx72 Module(1Rank of x4) - page2
- 8GB, 1Gx72 Module(2Rank of x8) - page1
- 8GB, 1Gx72(2Rank of x8) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page1
- 16GB, 2Gx72 Module(2Rank of x4) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page1
- 32GB, 4Gx72 Module(4Rank of x4) - page2
- 32GB, 4Gx72 Module(4Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page4
- 32GB, 4Gx72 Module(4Rank of x4) - page5
- Absolute Maximum Ratings
- AC & DC Operating Conditions
- AC & DC Input Measurement Levels
- Vref Tolerances
- AC and DC Logic Input Levels for Differential Signals
- Differential signal definition
- Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
- note : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VIL(ac) level.
- Single-ended requirements for differential signals
- Differential Input Cross Point Voltage
- Slew Rate Definitions for Single-Ended Input Signals
- Slew Rate Definitions for Differential Input Signals
- AC & DC Output Measurement Levels
- Overshoot and Undershoot Specifications
- Refresh parameters by device density
- Standard Speed Bins
- Environmental Parameters
- IDD and IDDQ Specification Parameters and Test Conditions
- IDD Specifications (Tcase: 0 to 95oC)
- Module Dimensions
Rev. 1.0 / May. 2014 22
32GB, 4Gx72 Module(4Rank of x4) - page3
ZQ
ARRASB
ARCASB
ARS0B
ARWEB
APCK0B
APCK0B
ARCKE0B
ARODT0B
ARA[N:O]B
Vtt
/ARBA[N:O]B
DQ[35:32]
DQS4
DQS4
DQS
DQS
DM
D11
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D10
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
D13
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D12
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D15
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D14
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D17
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D16
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
BRRASB
BRCASB
BRS2B
BRWEB
BPCK0B
BPCK0B
BRCKE0B
BRODT1B
BRA[N:O]B
/BRBA[N:O]B
DQS
DQS
DM
D13
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D42
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D41
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D40
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D39
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D38
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D37
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D36
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSSVSSVSSVSS
ARS1B
ARCKE1B
VDD
BRS3B
BRCKE1B
VDD
DQ[43:40]
DQS5
DQS5
DQS
DQS
DM
DQ [3:0]
ZQ
DQS
DQS
DM
DQ [3:0]
ZQ
VSS
DQS
DQS
DM
DQ [3:0]
ZQ
DQS
DQS
DM
DQ [3:0]
ZQVSSVSSVSSVSS
DQ[51:48]
DQS6
DQS6
DQS
DQS
DM
DQ [3:0]
DQS
DQS
DM
DQ [3:0]
ZQ
VSS
DQS
DQS
DM
DQ [3:0]
ZQ
DQS
DQS
DM
DQ [3:0]
ZQVSSVSSVSSVSS
DQ[59:56
DQS7
DQS7
DQS
DQS
DM
DQ [3:0]
ZQ
DQS
DQS
DM
DQ [3:0]
ZQ
VSS
DQS
DQS
DM
DQ [3:0]
ZQ
DQS
DQS
DM
DQ [3:0]
ZQVSSVSSVSSVSS
ZQ