Datasheet
Table Of Contents
- Description
- Features
- Ordering Information
- Key Parameters
- Speed Grade
- Address Table
- Pin Descriptions
- Input/Output Functional Descriptions
- Pin Assignments
- Registering Clock Driver Specifications
- On DIMM Thermal Sensor
- Functional Block Diagram
- 4GB, 512Mx72 Module(1Rank of x8)
- 8GB, 1Gx72 Module(1Rank of x4) - page1
- 8GB, 1Gx72 Module(1Rank of x4) - page2
- 8GB, 1Gx72 Module(2Rank of x8) - page1
- 8GB, 1Gx72(2Rank of x8) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page1
- 16GB, 2Gx72 Module(2Rank of x4) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page1
- 32GB, 4Gx72 Module(4Rank of x4) - page2
- 32GB, 4Gx72 Module(4Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page4
- 32GB, 4Gx72 Module(4Rank of x4) - page5
- Absolute Maximum Ratings
- AC & DC Operating Conditions
- AC & DC Input Measurement Levels
- Vref Tolerances
- AC and DC Logic Input Levels for Differential Signals
- Differential signal definition
- Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
- note : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VIL(ac) level.
- Single-ended requirements for differential signals
- Differential Input Cross Point Voltage
- Slew Rate Definitions for Single-Ended Input Signals
- Slew Rate Definitions for Differential Input Signals
- AC & DC Output Measurement Levels
- Overshoot and Undershoot Specifications
- Refresh parameters by device density
- Standard Speed Bins
- Environmental Parameters
- IDD and IDDQ Specification Parameters and Test Conditions
- IDD Specifications (Tcase: 0 to 95oC)
- Module Dimensions
Rev. 1.0 / May. 2014 18
16GB, 2Gx72 Module(2Rank of x4) - page2
D0–D35
V
DD
D0–D35
V
TT
V
DDSPD
D0–D35
VREFDQ
SPD
VREFCA
V
SS
D0–D35
D0–D35
Note:
1. DQ-to-I/O wiring may be changed within a nibble.
2. See wiring diagrams for all resistors values.
3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms.
VDDSPD
EVENT
SCL
SDA
SA0
SPD with
Integrated
TS
SA1
SA2
VSS
VDDSPD
EVENT
SCL
SDA
SA0
SA1
SA2
VSS
RRASB
RCASB
RS0B
RWEB
PCK0B
PCK0B
RCKE0B
RODT0B
A[N:O]B
/BA[N:O]B
DQ[47:44]
DQS14
DQS14
DQS
DQS
DM
D14
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D32
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQS4
DQS4
DQS
DQS
DM
D4
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
D22
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQS16
DQS16
DQS
DQS
DM
D16
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D34
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQS7
DQS7
DQS
DQS
DM
D7
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D25
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
Vtt
DQ[39:36]
DQS13
DQS13
DQS
DQS
DM
D13
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D31
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQ[43:40]
DQS5
DQS5
DQS
DQS
DM
D5
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
D23
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQ[55:52]
DQS15
DQS15
DQS
DQS
DM
D15
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D33
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQ[51:48]
DQS6
DQS6
DQS
DQS
DM
D6
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D24
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
RS1B
RCKE1B
R0DT1B
DM DM
Vtt
RRASB
RCASB
RS0B
RWEB
PCK0B
PCK0B
RCKE0B
RODT0B
A[N:O]B
/BA[N:O]B
RS
1B
RCKE1B
R0DT1B
PCK1
B
PCK1B
PCK1B
PCK1B
DQ[35:32]
DQ[63:60]
DQ[59:56]
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s requests. For more
details of SPD and Thermal sensor, please contact
local SK hynix sales representative