Datasheet
Table Of Contents
- Description
- Features
- Ordering Information
- Key Parameters
- Speed Grade
- Address Table
- Pin Descriptions
- Input/Output Functional Descriptions
- Pin Assignments
- Registering Clock Driver Specifications
- On DIMM Thermal Sensor
- Functional Block Diagram
- 4GB, 512Mx72 Module(1Rank of x8)
- 8GB, 1Gx72 Module(1Rank of x4) - page1
- 8GB, 1Gx72 Module(1Rank of x4) - page2
- 8GB, 1Gx72 Module(2Rank of x8) - page1
- 8GB, 1Gx72(2Rank of x8) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page1
- 16GB, 2Gx72 Module(2Rank of x4) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page1
- 32GB, 4Gx72 Module(4Rank of x4) - page2
- 32GB, 4Gx72 Module(4Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page4
- 32GB, 4Gx72 Module(4Rank of x4) - page5
- Absolute Maximum Ratings
- AC & DC Operating Conditions
- AC & DC Input Measurement Levels
- Vref Tolerances
- AC and DC Logic Input Levels for Differential Signals
- Differential signal definition
- Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
- note : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VIL(ac) level.
- Single-ended requirements for differential signals
- Differential Input Cross Point Voltage
- Slew Rate Definitions for Single-Ended Input Signals
- Slew Rate Definitions for Differential Input Signals
- AC & DC Output Measurement Levels
- Overshoot and Undershoot Specifications
- Refresh parameters by device density
- Standard Speed Bins
- Environmental Parameters
- IDD and IDDQ Specification Parameters and Test Conditions
- IDD Specifications (Tcase: 0 to 95oC)
- Module Dimensions
Rev. 1.0 / May. 2014 14
8GB, 1Gx72 Module(1Rank of x4) - page2
S0
S1
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
ODT0
CK0
CK0
PAR_IN
RS0A
→
CS0: SDRAMs D[3:0], D[12:8], D17
RS0B
→
CS0: SDRAMs D[7:4], D[16:13]
RRASB
→
RAS: SDRAMs D[7:4], D[16:13]
RBA[N:0]B
→
BA[N:0]: SDRAMs D[7:4], D[16:13]
RBA[N:0]A
→
BA[N:0]: SDRAMs D[3:0], D[12:8], D17
RRASA
→
RAS: SDRAMs D[3:0], D[12:8], D17
RCASB
→
CAS: SDRAMs D[7:4], D[16:13]
RCASA
→
CAS: SDRAMs D[3:0], D[12:8], D17
RWEB
→
WE: SDRAMs D[7:4], D[16:13]
RWEA
→
WE: SDRAMs D[3:0], D[12:8], D17
RCKE0B
→
CKE0: SDRAMs D[7:4], D[16:13]
RCKE0A
→
CKE0: SDRAMs D[3:0], D[12:8], D17
RODT0B
→
ODT0: SDRAMs D[7:4], D[16:13]
RODT0A
→
ODT0: SDRAMs D[3:0], D[12:8]. D17
PCK0B
→
CK: SDRAMs D[7:4]
PCK0A
→
CK: SDRAMs D[3:0], D8
PCK0B
→
CK: SDRAMs D[7:4]
PCK0A
→
CK: SDRAMs D[3:0], D8
Err_Out
OERR
RESET
RST
RST: SDRAMs D[17:0]
1:2
R
E
G
I
S
T
E
R
/
P
RA[N:0]B
→
A[N:0]: SDRAMs D[7:4], D[16:13]
RA[N:0]A
→
A[N:0]: SDRAMs D[3:0], D[12:8], D17
L
L
* S[3:2], CKE1, ODT1, CK1 and CK1 are NC (Unused register inputs ODT1 and CKE1 have a 330 resistor to ground.)
RS1A
→
CS1: SDRAMs D[12:9], D17
RS1B
→
CS1: SDRAMs D[16:13]