Datasheet
Table Of Contents
- Description
- Features
- Ordering Information
- Key Parameters
- Speed Grade
- Address Table
- Pin Descriptions
- Input/Output Functional Descriptions
- Pin Assignments
- Registering Clock Driver Specifications
- On DIMM Thermal Sensor
- Functional Block Diagram
- 4GB, 512Mx72 Module(1Rank of x8)
- 8GB, 1Gx72 Module(1Rank of x4) - page1
- 8GB, 1Gx72 Module(1Rank of x4) - page2
- 8GB, 1Gx72 Module(2Rank of x8) - page1
- 8GB, 1Gx72(2Rank of x8) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page1
- 16GB, 2Gx72 Module(2Rank of x4) - page2
- 16GB, 2Gx72 Module(2Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page1
- 32GB, 4Gx72 Module(4Rank of x4) - page2
- 32GB, 4Gx72 Module(4Rank of x4) - page3
- 32GB, 4Gx72 Module(4Rank of x4) - page4
- 32GB, 4Gx72 Module(4Rank of x4) - page5
- Absolute Maximum Ratings
- AC & DC Operating Conditions
- AC & DC Input Measurement Levels
- Vref Tolerances
- AC and DC Logic Input Levels for Differential Signals
- Differential signal definition
- Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
- note : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VIL(ac) level.
- Single-ended requirements for differential signals
- Differential Input Cross Point Voltage
- Slew Rate Definitions for Single-Ended Input Signals
- Slew Rate Definitions for Differential Input Signals
- AC & DC Output Measurement Levels
- Overshoot and Undershoot Specifications
- Refresh parameters by device density
- Standard Speed Bins
- Environmental Parameters
- IDD and IDDQ Specification Parameters and Test Conditions
- IDD Specifications (Tcase: 0 to 95oC)
- Module Dimensions
Rev. 1.0 / May. 2014 10
Registering Clock Driver Specifications
Capacitance Values
Input & Output Timing Requirements
Symbol Parameter Conditions Min Typ Max Unit
C
I
Input capacitance, Data inputs 1.5 - 2.5 pF
Input capacitance, CK, CK, FBIN, FBIN
(up to DDR3-1600)
1.5 - 2.5 pF
C
IR
Input capacitance, RESET, MIRROR,
QCSEN
V
I
= V
DD
or GND; V
DD
= 1.5v
--3pF
Symbol Parameter Conditions
DDR3-800
1066/1333
DDR3-1600 DDR3-1866
Unit
Min Max Min Max Min Max
f
clock
Input clock fre-
quency
Application fre-
quency
300 670 300 810 300 945 Mhz
f
TEST
Input clock fre-
quency
Test frequency 70 300 70 300 70 300 Mhz
t
SU
Setup time
Input valid before
CK/CK
100 - 50 - 40 - ps
t
H
Hold time
Input to remain
valid after CK/CK
175-125- 75 -ps
t
PDM
Propagation
delay, single-bit
switching
CK/CK
to output 0.65 1.0 0.65 1.0 0.65 1.0 ns
t
DIS
Output disable
time (1/2-Clock
prelaunch)
Yn/Yn
to output
float
0.5 +
tQSK1(min)
-
0.5 +
tQSK1(min)
-
0.5 +
tQSK1(min)
-ps
t
EN
Output enable
time (1/2-Clock
prelaunch)
Output driving to
Yn/Yn
0.5 -
tQSK1(max)
-
0.5 -
tQSK1(max)
-
0.5 -
tQSK1(max)
-ps