Datasheet

Rev. 1.0 / Jun. 2013 24
32GB, 4Gx72 Module(4Rank of x4) - page5
CK1
CK1
120 Ω
±5%
S2
S3
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
CK0
CK0
PAR_IN
BRS2A
→ CS1: SDRAMs D45,D47,D49,D51,D53
BRS2B → CS1: SDRAMs D37,D39,D41,D43,
BRS3A → CS0: SDRAMs D44.D46,D48,D50,D52,
BRRASB → RAS: SDRAMs D[43:36],D[61:54]
BRS3B → CS0: SDRAMs D36,D38,D40,D42,
BRBA[N:0]B → BA[N:0]: SDRAMs D[43:36],D[61:54]
BRBA[N:0]A → BA[N:0]: SDRAMs D[53:44],D[71:62]
BRRASA → RAS: SDRAMs D[53:44],D[71:62]
BRCASB → CAS: SDRAMs D[43:36],D[61:54]
BRCASA → CAS: SDRAMs D[53:44],D[71:62]
BRWEB → WE: SDRAMs D[43:36],D[61:54]
BRWEA → WE: SDRAMs D[53:44],D[71:62]
BRCKE0B → CKE1: SDRAMs D37,D39,D41,D43,
BRCKE0A → CKE1: SDRAMs D45,D47,D49,D51,D53,
BRODT1B → ODT0: SDRAMs D37,D39,D41,D43
BRODT1A → ODT1: SDRAMs D45,D47,D49,D51,D53
BPCK0B → CK: SDRAMs D[43:36]
BPCK0A → CK: SDRAMs D[53:44]
BPCK0B → CK: SDRAMs D[43:36]
BPCK0A → CK: SDRAMs D[53:44]
Err_Out
RESET RST
1:2
R
E
G
I
S
T
E
R
/
P
BRCKE1B → CKE0: SDRAMs D36,D38,D40,D42,
BRCKE1A → CKE0: SDRAMs D44.D46,D48,D50,D52,
ODT1
CKE1
BRA[N:0]B
→ A[N:0]: SDRAMs D[43:36],D[61:54]
BRA[N:0]A → A[N:0]: SDRAMs D[55:44],D[71:62]
BPCK1B → CK: SDRAMs D[61:54]
BPCK1A → CK: SDRAMs D[71:62]
BPCK1B → CK: SDRAMs D[61:54]
BPCK1A → CK: SDRAMs D[71:62]
L
L
B
D63,D65,D67,D69,D71
D55,D57,D59,D61
D62,D64,D66,D68,D70
D54,D56,D58,D60
D63,D65,D67,D69,D71
D55,D57,D59,D61
D62,D64,D66,D68,D70
D54,D56,D58,D60
D63,D65,D67,D69,D71
D55,D57,D59,D61
120 Ω
±5%
S0
S1
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
CK0
CK0
PAR_IN
ARS0A
→ CS1: SDRAMs D1,D3,D5,D7 D9,
ARS0B → CS1: SDRAMs D11, D13, D15, D17,
ARS1A → CS0: SDRAMs D0, D2, D4, D6, D8,
ARRASB → RAS: SDRAMs D[17:10],D[35:28]
ARS1B → CS0: SDRAMs D10, D12, D14, D16,
ARBA[N:0]B → BA[N:0]: SDRAMs D[17:10],D[35:28]
ARBA[N:0]A → BA[N:0]: SDRAMs D[9:0],D[27:18]
ARRASA → RAS: SDRAMs D[9:0],D[27:18]
ARCASB → CAS: SDRAMs D[17:10],D[35:28]
ARCASA → CAS: SDRAMs D[9:0],D[27:18]
ARWEB → WE: SDRAMs D[17:10],D[35:28]
ARWEA → WE: SDRAMs D[9:0],D[27:18]
ARCKE0B → CKE1: SDRAMs D11,D13,D15,D17,
ARCKE0A → CKE1: SDRAMs D1,D3,D5,D7,D9,
ARODT0B → ODT0: SDRAMs D11,D13,D15,D17,
ARODT0A → ODT1: SDRAMs D1,D3,D5,D7,D9,
APCK0B → CK: SDRAMs D[17:10]
APCK0A → CK: SDRAMs D[9:0]
APCK0B → CK: SDRAMs D[17:10]
APCK0A → CK: SDRAMs D[9:0]
Err_Out
RESET RST
RST: SDRAMs D[35:0]
1:2
R
E
G
I
S
T
E
R
/
P
ARCKE1B → CKE0: SDRAMs D10,D12,D14,D16,
ARCKE1A → CKE0: SDRAMs D0,D2,D4,D6,D8,
ODT0
CKE1
ARA[N:0]B
→ A[N:0]: SDRAMs D[17:10],D[35:28]
ARA[N:0]A → A[N:0]: SDRAMs D[9:0],D[27:18]
APCK1B → CK: SDRAMs D[35:28]
APCK1A → CK: SDRAMs D[27:18]
APCK1B → CK: SDRAMs D[35:28]
APCK1A → CK: SDRAMs D[27:18]
L
L
A
D19, D21, D23, D25, D27
D29, D31, D33, D35
D18, D20, D22, D24, D26
D28, D30, D32, D34
D19, D21, D23, D25, D27
D29, D31, D33, D35
D18, D20, D22, D24, D26
D28, D30, D32, D34
D19, D21, D23, D25, D27
D29, D31, D33, D35
120 Ω
±5%
1. CK0 and CK0 are differentially terminated with a single 120 Ohms ±5% resistor.
2.
CK1 and CK1 are differentially terminated with a single 120 Ohms ±5% resistor, but is not used.
3. Unused register inputs ODT1 for Register A and ODT0 for Register B are tied to ground.
4. The module drawing on this page is not drawn to scale.