Datasheet

Rev. 1.0/Sep. 2012 5
Pin Descriptions
Pin Name Description
Num
ber
Pin Name Description
Num
ber
CK[1:0] Clock Input, positive line 2 DQ[63:0] Data Input/Output 64
CK
[1:0] Clock Input, negative line 2 DM[7:0] Data Masks 8
CKE[1:0] Clock Enables 2 DQS[7:0] Data strobes 8
RAS
Row Address Strobe 1 DQS[7:0] Data strobes, negative line 8
CAS
Column Address Strobe 1 EVENT Temperature event pin 1
WE
Write Enable 1 TEST
Logic Analyzer specific test pin (No
connect on SODIMM)
1
S
[1:0] Chip Selects 2 RESET Reset Pin 1
A[9:0],A11,
A[15:13]
Address Inputs 14
V
DD
Core and I/O Power 18
A10/AP Address Input/Autoprecharge 1
V
SS
Ground 52
A12/BC
Address Input/Burst chop 1
BA[2:0] SDRAM Bank Addresses 3
V
REFDQ
Input/Output Reference
1
ODT[1:0] On Die Termination Inputs 2
V
REFCA
1
SCL
Serial Presence Detect (SPD)
Clock Input
1
V
TT
Termination Voltage 2
SDA SPD Data Input/Output 1
V
DDSPD
SPD Power 1
SA[1:0] SPD Address Inputs 2 NC Reserved for future use 2
Total:
204