Datasheet
Table Of Contents
- Description
- Fetures
- Ordering Information
- Key Parameters
- Speed Grade
- Address Table
- Pin Descriptions
- Input/Output Functional Descriptions
- Pin Assignments
- Functional Block Diagram
- Absolute Maximum Ratings
- AC & DC Operating Conditions
- AC & DC Input Measurement Levels
- Vref Tolerances
- AC and DC Logic Input Levels for Differential Signals
- AC & DC Output Measurement Levels
- Overshoot and Undershoot Specifications
- Refresh parameters by device density
- Standard Speed Bins
- IDD and IDDQ Specification Parameters and Test Conditions
- IDD Specifications (Tcase: 0 to 95oC)
- Module Dimensions
Rev. 1.0/Sep. 2012 4
Key Parameters
*SK hynix DRAM devices support optional downbinning to CL11, CL9 and CL7. SPD setting is programmed
to match.
Speed Grade
Address Table
MT/s Grade
tCK
(ns)
CAS
Latency
(tCK)
tRCD
(ns)
tRP
(ns)
tRAS
(ns)
tRC
(ns)
CL-tRCD-tRP
DDR3-1066 -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7
DDR3-1333 -H9 1.5 9
13.5
(13.125)*
13.5
(13.125)*
36
49.5
(49.125)*
9-9-9
DDR3-1600 -PB 1.25 11
13.75
(13.125)*
13.75
(13.125)*
35
48.75
(48.125)*
11-11-11
Grade
Frequency [MHz]
Remark
CL5 CL6 CL7 CL8 CL9 CL10 CL11
-G7 667 800 1066 1066
-H9 667 800 1066 1066 1333 1333
-PB 667 800 1066 1066 1333 1333 1600
2GB(1Rx8) 4GB(2Rx8)
Refresh Method 8K/64ms 8K/64ms
Row Address A0-A14 A0-A14
Column Address A0-A9 A0-A9
Bank Address BA0-BA2 BA0-BA2
Page Size 1KB 1KB