Datasheet

Rev. 1.0/Sep. 2012 38
I
DD4R
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: High between RD; Command, Address,
Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open,
RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode
Registers
b)
; ODT Signal: stable at 0; Pattern Details: see Table 7.
I
DD4W
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open,
WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode
Registers
b)
; ODT Signal: stable at HIGH; Pattern Details: see Table 8.
I
DD5B
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8
a)
; AL: 0; CS: High between REF; Command,
Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0;
Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registers
b)
;
ODT Signal: stable at 0; Pattern Details: see Table 9.
I
DD6
Self-Refresh Current: Normal Temperature Range
T
CASE
: 0 - 85
o
C; Auto Self-Refresh (ASR): Disabled
d)
;Self-Refresh Temperature Range (SRT): Normal
e)
; CKE:
Low; External clock: Off; CK and CK
: LOW; CL: see Table 1; BL: 8
a)
; AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer
and RTT: Enabled in Mode Registers
b)
; ODT Signal: MID_LEVEL
I
DD6ET
Self-Refresh Current: Extended Temperature Range
T
CASE
: 0 - 95
o
C; Auto Self-Refresh (ASR): Disabled
d)
;Self-Refresh Temperature Range (SRT): Extended
e)
;
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8
a)
; AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode Registers
b)
; ODT Signal: MID_LEVEL
Symbol Description