Datasheet
Table Of Contents
- Description
- Fetures
- Ordering Information
- Key Parameters
- Speed Grade
- Address Table
- Pin Descriptions
- Input/Output Functional Descriptions
- Pin Assignments
- Functional Block Diagram
- Absolute Maximum Ratings
- AC & DC Operating Conditions
- AC & DC Input Measurement Levels
- Vref Tolerances
- AC and DC Logic Input Levels for Differential Signals
- AC & DC Output Measurement Levels
- Overshoot and Undershoot Specifications
- Refresh parameters by device density
- Standard Speed Bins
- IDD and IDDQ Specification Parameters and Test Conditions
- IDD Specifications (Tcase: 0 to 95oC)
- Module Dimensions

Rev. 1.0/Sep. 2012 31
DDR3-1333 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 33.
Speed Bin DDR3-1333H
Unit Note
CL - nRCD - nRP 9-9-9
Parameter Symbol min max
Internal read
command to first data
t
AA
13.5
(13.125)
5,9
20 ns
ACT to internal read or
write delay time
t
RCD
13.5
(13.125)
5,9
—ns
PRE command period
t
RP
13.5
(13.125)
5,9
—ns
ACT to ACT or REF
command period
t
RC
49.5
(49.125)
5,9
—ns
ACT to PRE command
period
t
RAS
36 9 * tREFI ns
CL = 5
CWL = 5
t
CK(AVG)
3.0 3.3 ns 1, 2, 3, 4, 7, 10
CWL = 6, 7
t
CK(AVG)
Reserved ns 4
CL = 6
CWL = 5
t
CK(AVG)
2.5 3.3 ns 1, 2, 3, 7
CWL = 6
t
CK(AVG)
Reserved ns 1, 2, 3, 4, 7
CWL = 7
t
CK(AVG)
Reserved ns 4
CL = 7
CWL = 5
t
CK(AVG)
Reserved ns 4
CWL = 6
t
CK(AVG)
1.875 < 2.5
ns 1, 2, 3, 4, 7
(Optional)
5,9
CWL = 7
t
CK(AVG)
Reserved ns 1, 2, 3, 4
CL = 8
CWL = 5
t
CK(AVG)
Reserved ns 4
CWL = 6
t
CK(AVG)
1.875 < 2.5 ns 1, 2, 3, 7
CWL = 7
t
CK(AVG)
Reserved ns 1, 2, 3, 4
CL = 9
CWL = 5, 6
t
CK(AVG)
Reserved ns 4
CWL = 7
t
CK(AVG)
1.5 <1.875 ns 1, 2, 3, 4
CL = 10
CWL = 5, 6
t
CK(AVG)
Reserved ns 4
CWL = 7
t
CK(AVG)
1.5 <1.875 ns 1, 2, 3
(Optional) ns 5
Supported CL Settings 5, 6, 8, (7), 9, (10)
n
CK
Supported CWL Settings 5, 6, 7
n
CK