204pin DDR3 SDRAM SODIMM DDR3 SDRAM Unbuffered SODIMMs Based on 2Gb C-die HMT325S6CFR8C HMT351S6CFR8C *SK hynix reserves the right to change products or specifications without notice. Rev. 1.0 / Sep.
Revision History Revision No. History Draft Date Remark 0.1 Initial Release Mar.2011 Preliminary 0.2 IDD Update Aug.2011 0.3 JEDEC SPEC Update Feb.2012 0.4 JEDEC SPEC Update Jun.2012 Rev. 1.0/Sep.
Description SK hynix Unbuffered Small Outline DDR3 SDRAM DIMMs (Unbuffered Small Outline Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use DDR3 SDRAM devices. These Unbuffered DDR3 SDRAM SODIMMs are intended for use as main memory when installed in systems such as mobile personal computers. Fetures • VDD=1.5V +/- 0.075V • VDDQ=1.5V +/- 0.075V • VDDSPD=3.0V to 3.
Key Parameters MT/s Grade tCK (ns) CAS Latency (tCK) tRCD (ns) tRP (ns) tRAS (ns) tRC (ns) CL-tRCD-tRP DDR3-1066 -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7 DDR3-1333 -H9 1.5 9 13.5 13.5 (13.125)* (13.125)* 36 49.5 (49.125)* 9-9-9 DDR3-1600 -PB 1.25 11 13.75 13.75 (13.125)* (13.125)* 35 48.75 (48.125)* 11-11-11 *SK hynix DRAM devices support optional downbinning to CL11, CL9 and CL7. SPD setting is programmed to match.
Pin Descriptions Pin Name Description Num ber Pin Name Num ber Description CK[1:0] Clock Input, positive line 2 DQ[63:0] Data Input/Output 64 CK[1:0] Clock Input, negative line 2 DM[7:0] Data Masks 8 CKE[1:0] Clock Enables 2 DQS[7:0] Data strobes 8 RAS Row Address Strobe 1 DQS[7:0] Data strobes, negative line 8 CAS Column Address Strobe 1 EVENT Temperature event pin 1 WE Write Enable 1 TEST S[1:0] Chip Selects 2 RESET Address Inputs 14 A10/AP Address Input/Auto
Input/Output Functional Descriptions Symbol Type Polarity Function The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is Cross Point driven from the clock inputs and output timing for read operations is synchronized to the input clock.
Symbol Type Polarity Function SDA I/O — This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pullup. SCL IN — This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDDSPD on the system planar to act as a pullup.
Pin Assignments Pin # Front Side Pin # Back Side Pin # Front Side Pin # Back Side Pin # Front Side Pin # Back Side Pin # Front Side Pin # Back Side 1 VREFDQ 2 VSS 53 DQ19 54 VSS 105 VDD 106 VDD 157 DQ42 158 DQ46 3 VSS 4 DQ4 55 VSS 56 DQ28 107 A10/AP 108 BA1 159 DQ43 160 DQ47 5 DQ0 6 DQ5 57 DQ24 58 DQ29 109 BA0 110 RAS 161 VSS 162 VSS 7 DQ1 8 VSS 59 DQ25 60 VSS 111 VDD 112 VDD 163 DQ48 164 DQ52 9 VSS 10 DQS0 61 VSS 62 DQS3
Functional Block Diagram 240ohm +/-1% SCL A0 Temp Sensor (with SPD) A1 A2 EVENT SCL SA0 SA1 A[O:N]/BA[O:N] ODT EVENT CK CKE SCL A0 A1 A2 SCL SA0 SA1 The SPD may be integrated with the Temp Sensor or may be a separate component (SPD) SDA WP Vtt LDQS LDQS LDM DQ [0:7] ZQ A[O:N]/BA[O:N] ODT CK CKE CK WE D5 A[O:N]/BA[O:N] ODT CK CKE WE SPD/TS VREFCA VREFDQ D0–D7 D0–D7 VSS D0–D7, SPD, Temp sensor CK0 D0–D7 CK0 D0–D7 CK1 S1 NC ODT1 CKE1 NC EVENT Temp Sensor RESET D0-D7
SCL SA0 SA1 SCL A0 A1 A2 (SPD) D8 SDA D0 Rev. 1.0/Sep. 2012 V1 V9 D12 V8 Rank 0 Rank 1 D1 D6 V7 V4 V4 V5 D10 V5 D2 D5 D13 V6 V6 Vtt V3 EVENT NOTES 1.
Absolute Maximum Ratings Absolute Maximum DC Ratings Absolute Maximum DC Ratings Symbol VDD VDDQ Parameter Rating Units Notes Voltage on VDD pin relative to Vss - 0.4 V ~ 1.8 V V 1,3 Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.8 V V 1,3 V 1 VIN, VOUT Voltage on any pin relative to Vss TSTG - 0.4 V ~ 1.8 V -55 to +100 Storage Temperature o C 1, 2 Notes: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
AC & DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions Symbol VDD VDDQ Parameter Rating Units Notes 1.575 V 1,2 1.575 V 1,2 Min. Typ. Max. Supply Voltage 1.425 1.500 Supply Voltage for Output 1.425 1.500 Notes: 1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. Rev. 1.0/Sep.
AC & DC Input Measurement Levels AC and DC Logic Input Levels for Single-Ended Signals AC and DC Input Levels for Single-Ended Command and Address Signals Single Ended AC and DC Input Levels for Command and ADDress Symbol Parameter VIH.CA(DC100) VIL.CA(DC100) VIH.CA(AC175) VIL.CA(AC175) VIH.CA(AC150) VIL.CA(AC150) VIH.CA(AC135) VIL.CA(AC135) VIH.CA(AC125) VIL.
AC and DC Input Levels for Single-Ended Signals DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as specified in the table below. DDR3 SDRAM will also support corresponding tDS values (Table 43 and Table 51 in “ DDR3 Device Operation”) as well as derating tables in Table 46 of “DDR3 Device Operation” depending on Vih/Vil AC levels. Single Ended AC and DC Input Levels for DQ and DM Symbol Parameter VIH.DQ(DC100) VIL.DQ(DC100) VIH.DQ(AC175) VIL.DQ(AC175) VIH.DQ(AC150) VIL.
Vref Tolerances The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure below. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise). VRef (DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in the table "Differential Input Slew Rate Definition" on page 21.
AC and DC Logic Input Levels for Differential Signals Differential signal definition tDVAC Differential Input Voltage(i.e.DQS - DQS#, CK - CK#) VIL.DIFF.AC.MIN VIL.DIFF.MIN 0 half cycle VIL.DIFF.MAX VIL.DIFF.AC.MAX tDVAC time Definition of differential ac-swing and “time above ac-level” tDVAC Rev. 1.0/Sep.
Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS) Differential AC and DC Input Levels DDR3-800, 1066, 1333, & 1600 Symbol Parameter VIHdiff VILdiff Differential input high Differential input logic low Differential input high ac Differential input low ac VIHdiff (ac) VILdiff (ac) Min Max + 0.200 Note 3 2 x (VIH (ac) - Vref) Note 3 Note 3 - 0.200 Note 3 2 x (VIL (ac) - Vref) Unit Notes V V V V 1 1 2 2 Notes: 1. Used to define a differential signal slew-rate. 2.
Single-ended requirements for differential signals Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH (ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle.
Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU Symbol VSEH VSEL DDR3-800, 1066, 1333, & 1600 Parameter Single-ended high level for strobes Single-ended high level for Ck, CK Single-ended low level for strobes Single-ended low level for CK, CK Min Max (VDD / 2) + 0.175 (VDD /2) + 0.175 Note 3 Note 3 Note 3 Note 3 (VDD / 2) - 0.175 (VDD / 2) - 0.175 Unit Notes V V V V 1,2 1,2 1,2 1,2 Notes: 1.
Cross point voltage for differential input signals (CK, DQS) Symbol Parameter VIX(CK) VIX(DQS) DDR3-800, 1066, 1333, 1600 Unit Notes Min Max Differential Input Cross Point Voltage relative to VDD/2 for CK, CK -150 -175 150 175 mV mV 2 1 Differential Input Cross Point Voltage relative to VDD/2 for DQS, DQS -150 150 mV 2 Notes: 1.
Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in table and figure below.
AC & DC Output Measurement Levels Single Ended AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals.
Single Ended Output Slew Rate When the Reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals are shown in table and figure below.
Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and Figure below.
Reference Load for AC Timing and Output Slew Rate Figure below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment.
Overshoot and Undershoot Specifications Address and Control Overshoot and Undershoot Specifications AC Overshoot/Undershoot Specification for Address and Control Pins DDR3- DDR3- DDR3- DDR3- 800 1066 1333 1600 Maximum peak amplitude allowed for overshoot area. (See Figure below) 0.4 0.4 0.4 0.4 V Maximum peak amplitude allowed for undershoot area. (See Figure below) 0.4 0.4 0.4 0.4 V Maximum overshoot area above VDD (See Figure below) 0.67 0.5 0.4 0.
Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask DDR3- DDR3- DDR3- DDR3- Parameter Maximum peak amplitude allowed for overshoot area. (See Figure below) Maximum peak amplitude allowed for undershoot area. (See Figure below) Maximum overshoot area above VDD (See Figure below) Maximum undershoot area below VSS (See Figure below) 800 1066 1333 1600 0.4 0.4 0.25 0.25 0.4 0.4 0.19 0.19 0.4 0.4 0.15 0.15 0.4 0.4 0.
Refresh parameters by device density Refresh parameters by device density Parameter REF command ACT or REF command time Average periodic refresh interval Rev. 1.0/Sep. 2012 RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units tRFC 90 110 160 260 350 ns 7.8 7.8 7.8 7.8 7.8 us 3.9 3.9 3.9 3.9 3.
Standard Speed Bins DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin. DDR3-800 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 33. Speed Bin DDR3-800E CL - nRCD - nRP 6-6-6 Unit Notes Parameter Symbol min max Internal read command to first data tAA 15 20 ns ACT to internal read or write delay time tRCD 15 — ns PRE command period tRP 15 — ns ACT to ACT or REF command period tRC 52.
DDR3-1066 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 33. Speed Bin DDR3-1066F CL - nRCD - nRP Parameter Symbol Unit 7-7-7 min max Note Internal read command to first data tAA 13.125 20 ns ACT to internal read or write delay time tRCD 13.125 — ns PRE command period tRP 13.125 — ns ACT to ACT or REF command period tRC 50.625 — ns ACT to PRE command period tRAS 37.5 9 * tREFI ns CWL = 5 tCK(AVG) 3.0 3.
DDR3-1333 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 33. Speed Bin DDR3-1333H CL - nRCD - nRP Parameter Symbol Unit 9-9-9 min max Note Internal read command to first data tAA 13.5 (13.125)5,9 20 ns ACT to internal read or write delay time tRCD 13.5 (13.125)5,9 — ns PRE command period tRP 13.5 (13.125)5,9 — ns ACT to ACT or REF command period tRC 49.5 (49.125)5,9 — ns ACT to PRE command period tRAS 36 9 * tREFI ns CWL = 5 tCK(AVG) 3.0 3.
DDR3-1600 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 33. Speed Bin DDR3-1600K CL - nRCD - nRP Parameter Symbol Unit 11-11-11 min max Internal read command to first data tAA 13.75 (13.125)5,9 20 ns ACT to internal read or write delay time tRCD 13.75 (13.125)5,9 — ns PRE command period tRP 13.75 (13.125)5,9 — ns ACT to ACT or REF command period tRC 48.75 (48.125)5,9 — ns ACT to PRE command period tRAS 35 9 * tREFI ns CWL = 5 tCK(AVG) 3.0 3.
Speed Bin Table Notes Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V); 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed.
IDD and IDDQ Specification Parameters and Test Conditions IDD and IDDQ Measurement Conditions In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 1. shows the setup and test load for IDD and IDDQ measurements. • IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together.
IDDQ (optional) IDD VDD VDDQ RESET CK/CK DDR3 SDRAM CKE CS RAS, CAS, WE DQS, DQS DQ, DM, TDQS, TDQS A, BA ODT ZQ VSS RTT = 25 Ohm VDDQ/2 VSSQ Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements [Note: DIMM level Output test load condition may be different from above Application specific memory channel environment IDDQ Test Load Channel IO Power Simulation IDDQ Simulation IDDQ Simulation Correction Channel IO Power Number Figure 2 - Correlation from simulate
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns Symbol tCK DDR3-1066 DDR3-1333 DDR3-1600 7-7-7 9-9-9 11-11-11 1.875 1.5 1.
Symbol Description Precharge Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank IDD2N Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5.
Symbol Description Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address, IDD4R Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...
Symbol Description Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a,f); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table IDD7 10; Data IO: read data burst with different data between one burst and the next one according to Table 10; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...
Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 ACT 0 0 1 1 0 0 00 0 0 0 0 - 1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 0 0 - 0 0 0 - 0 F 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 3 - IDD0 Measurement-Loop Patterna) 0 3,4 ... nRAS ... Static High toggling 1*nRC+0 repeat pattern 1...4 until nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 00 0 repeat pattern 1...
Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 ACT 0 0 1 1 0 0 00 0 0 0 0 - 1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 0 0 - 0 0 00000000 0 0 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 4 - IDD1 Measurement-Loop Patterna) 0 3,4 ... nRCD ... nRAS Static High toggling ... repeat pattern 1...4 until nRCD - 1, truncate if necessary RD 0 1 0 1 0 0 00 0 0 repeat pattern 1...
Static High CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 D 1 0 0 0 0 0 0 0 0 0 0 - 1 D 1 0 0 0 0 0 0 0 0 0 0 - 2 D 1 1 1 1 0 0 0 0 0 F 0 - 3 D 1 1 1 1 0 0 0 0 0 F 0 - Cycle Number Command 0 toggling Datab) Sub-Loop CKE CK, CK Table 5 - IDD2N and IDD3N Measurement-Loop Patterna) 1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 8-11 repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 12-15 repeat Sub-Loop 0, use
Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 RD 0 1 0 1 0 0 00 0 0 0 0 00000000 1 D 1 0 0 0 0 0 00 0 0 0 0 - 2,3 D,D 1 1 1 1 0 0 00 0 0 0 0 - 4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011 D 1 0 0 0 0 0 00 0 0 F 0 - D,D 1 1 1 1 0 0 00 0 0 F 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna) 0 Static High toggling 5 6,7 1 8-15 repeat Sub-Loop
Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 0 REF 0 0 0 1 0 0 0 0 0 0 0 - 1 1.2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 F 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 9 - IDD5B Measurement-Loop Patterna) 3,4 Static High toggling 5...8 2 repeat cycles 1...4, but BA[2:0] = 1 9...12 repeat cycles 1...4, but BA[2:0] = 2 13...16 repeat cycles 1...4, but BA[2:0] = 3 17...20 repeat cycles 1...
Table 10 - IDD7 Measurement-Loop Patterna) 2 3 4 Static High 5 6 7 8 9 10 4*nRRD nFAW nFAW+nRRD nFAW+2*nRRD nFAW+3*nRRD nFAW+4*nRRD 2*nFAW+0 2*nFAW+1 2&nFAW+2 11 2*nFAW+nRRD 2*nFAW+nRRD+1 2&nFAW+nRRD+2 12 13 2*nFAW+2*nRRD 2*nFAW+3*nRRD 14 2*nFAW+4*nRRD 15 16 17 18 3*nFAW 3*nFAW+nRRD 3*nFAW+2*nRRD 3*nFAW+3*nRRD 19 3*nFAW+4*nRRD 00110011 - 0 - 0 - 0 0 0 00110011 - 0 0 0 00000000 - 0 - 0 - A[10] 0 0 0 ODT 00000000 - WE 0 0 0 CAS ACT 0 0 1 1 0 0 00 0 0 0 RDA 0 1 0 1 0 0 00 1
IDD Specifications (Tcase: 0 to 95oC) * Module IDD values in the datasheet are only a calculation based on the component IDD spec. The actual measurements may vary according to DQ loading cap.
Module Dimensions 256Mx64 - HMT325S6CFR8C Front Side 67.60mm 3.80mm max 30.0mm 2.0 Detail-A pin 1 2.15 2 X 1.80 0.10 pin 203 21.00 20.0mm 6.00 SPD 1.00 0.08 mm 39.00 1.65 0.10 3.00 Back 0.3~1.0 0.45 0.03 0.60 2.55 0.3 0.15 4.00 0.10 Detail of Contacts A 1.00 0.05 Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters Rev. 1.0/Sep.
512Mx64 - HMT351S6CFR8C Front Side 67.60mm 3.80mm max 2.0 Detail-B pin 1 pin 203 21.00 1.65 0.10 2.15 2 X 1.80 0.10 20.0mm Detail- A 6.00 30.0mm 4.00 0.10 1.00 0.08 mm 39.00 3.00 Back SPD 2.55 0.3 0.15 4.00 0.10 Detail of Contacts A 0.3~1.0 0.45 0.03 0.60 1.00 0.05 Note: 1. 0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters Rev. 1.0/Sep.