Datasheet
Rev. 1.1 / May. 2013 55
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol
DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866
Unit
7-7-7 9-9-9 11-11-11 13-13-13
t
CK
1.875 1.5 1.25 1.071 ns
CL 7 9 11 13 nCK
n
RCD
7 9 11 13 nCK
n
RC
27 33 39 45 nCK
n
RAS
20 24 28 32 nCK
n
RP
7 9 11 13 nCK
n
FAW
1KB page size 20 20 24 26 nCK
2KB page size 27 30 32 33 nCK
n
RRD
1KB page size 4 4 5 5 nCK
2KB page size 6 5 6 6 nCK
n
RFC
-512Mb 48 60 72 85 nCK
n
RFC
-1 Gb 59 74 88 103 nCK
n
RFC
- 2 Gb 86 107 128 150 nCK
n
RFC
- 4 Gb 139 174 208 243 nCK
n
RFC
- 8 Gb 187 234 280 328 nCK
Symbol Description
I
DD0
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8
a)
; AL: 0; CS: High between ACT and
PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;
DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buf-
fer and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0; Pattern Details: see Table 3.
I
DD1
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8
a)
; AL: 0; CS: High between ACT,
RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM:
stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and
RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0; Pattern Details: see Table 4.