Datasheet

Rev. 0.3 / Dec. 2009 16
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
Electrical Characteristics & AC Timings
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
AC Timing Parameters by Speed Grade
Speed DDR2-800 (S5) DDR2-800 (S6) DDR2-667 (Y5) DDR2-533 (C4) Unit
Bin (CL-tRCD-tRP) 5-5-5 6-6-6 5-5-5 4-4-4
Parameter min min min min
CAS Latency 5 6 5 4 tCK
tRCD 12.5 15 15 15 ns
tRP 12.5 15 15 15 ns
tRAS 45 45 45 45 ns
tRC 57.5 60 60 60 ns
Parameter Symbol
DDR2-400 DDR2-533
Unit Note
Min Max Min Max
Data-Out edge to Clock edge Skew tAC -600 600 -500 500 ps
DQS-Out edge to Clock edge Skew tDQSCK -500 500 -450 450 ns
Clock High Level Width tCH 0.45 0.55 0.45 0.55 CK
Clock Low Level Width tCL 0.45 0.55 0.45 0.55 CK
Clock Half Period tHP
min
(tCL, tCH)
-
min
(tCL, tCH)
-ns
System Clock Cycle Time tCK 5000 8000 3750 8000 ps
DQ and DM input setup time tDS 150 - 100 - ps 1
DQ and DM input hold time tDH 275 - 225 - ps 1
DQ and DM input setup time (single-ended strobe) tDS1 25 - -25 - ps 1
DQ and DM input hold time (single-ended strobe) tDH1 25 - -25 - ps 1
Control & Address input Pulse Width for each input tIPW 0.6 - 0.6 - tCK
DQ and DM input pulse width for each input pulse
width for each input
tDIPW 0.35 - 0.35 - tCK
Data-out high-impedance window from CK, /CK tHZ
- tAC max - tAC max
ps
DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps
DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps
DQS-DQ skew for DQS and associated DQ signals tDQSQ - 350 -300ps
DQ hold skew factor tQHS - 450 -400ps
DQ/DQS output hold time from DQS tQH tHP - tQHS - tHP - tQHS - ps
First DQS latching transition to associated clock
edge
tDQSS -0.25 +0.25 -0.25 +0.25 tCK
DQS input high pulse width tDQSH 0.35 - 0.35 - tCK
DQS input low pulse width tDQSL 0.35 - 0.35 - tCK
DQS falling edge to CK setup time tDSS 0.2 - 0.2 - tCK
DQS falling edge hold time from CK tDSH 0.2 - 0.2 - tCK
Mode register set command cycle time tMRD 2 - 2 - tCK
Write preamble tWPRE 0.35 - 0.35 - tCK
Write postamble tWPST 0.4 0.6 0.4 0.6 tCK
Data-Out edge to Clock edge Skew tAC -600 600 -500 500 ps
Address and control input setup time tIS 350 -250- ps