Datasheet

ManualsBrandsHynix Manualscomputer componentsHMP112S6EFR6C-Y5

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.3 / Dec. 2009 1

200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 1Gb version E

This Hynix unbuffered Small Outline Dual In-Line Memory Module (DIMM) series consists of 1Gb version E DDR2

SDRAMs in Fine Ball Grid Array (FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 1Gb version E based

Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of indus-

try standard. It is suitable for easy interchange and addition.

FEATURES

* This product is in compliance with the directive pertaining of RoHS

ORDERING INFORMATION

Part Name Density Organization

# of

DRAMs

# of

ranks

Materials

HMP164S6EFR6C-C4/Y5/S5/S6 512MB 64Mx64 4 1 Halogen free

HMP112S6EFR6C-C4/Y5/S5/S6 1GB 128Mx64 8 2 Halogen free

HMP125S6EFR8C-C4/Y5/S5/S6 2GB 256Mx64 16 2 Halogen free

• JEDEC standard Double Data Rate 2 Synchronous

DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power

Supply

• All inputs and outputs are compatible with SSTL_1.8

interface

•Posted CAS

• Programmable CAS Latency 3,4,5, and 6

• OCD (Off-Chip Driver Impedance Adjustment) and

ODT (On-Die Termination)

• Fully differential clock operations (CK & CK

)

• Programmable Burst Length 4 / 8 with both

sequential and interleave mode

• Auto refresh and self refresh supported

• 8192 refresh cycles / 64ms

• Serial presence detect with EEPROM

• DDR2 SDRAM Package: 60 ball(x8), 84 ball(x16)

FBGA

• 67.60 x 30.00 mm form factor

•RoHS compliant & Halogen-free

Summary of content (23 pages)

PAGE 1
200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 1Gb version E This Hynix unbuffered Small Outline Dual In-Line Memory Module (DIMM) series consists of 1Gb version E DDR2 SDRAMs in Fine Ball Grid Array (FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 1Gb version E based Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is suitable for easy interchange and addition.
PAGE 2
1200pin Unbuffered DDR2 SDRAM SO-DIMMs SPEED GRADE & KEY PARAMETERS C4 (DDR2-533) Y5 (DDR2-667) S6 (DDR2-800) S5 (DDR2-800) Unit Speed@CL3 400 400 - 400 Mbps Speed@CL4 533 533 533 533 Mbps Speed@CL5 - 667 667 800 Mbps Speed@CL6 - - 800 - Mbps CL-tRCD-tRP 4-4-4 5-5-5 6-6-6 5-5-5 tCK ADDRESS TABLE Density Organization Ranks SDRAMs # of DRAMs # of row/bank/column Address Refresh Method 512MB 64M x 64 1 64Mb x 16 4 13(A0~A12)/3(BA0~BA2)/10(A0~A9) 8K / 64ms 1GB 128
PAGE 3
1200pin Unbuffered DDR2 SDRAM SO-DIMMs PIN DESCRIPTION Symbol Type Polarity Pin Description The system clock inputs. All address an commands lines are sampled on the cross point CK[1:0], CK[1:0] Input Cross of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is Point driven from the clock inputs and output timing for read operations is synchronized to the input clock.
PAGE 4
1200pin Unbuffered DDR2 SDRAM SO-DIMMs PIN ASSIGNMENT Pin NO. Front Side Pin NO. Back Side Pin NO. Front Side Pin NO. Back Side Pin NO. Front Side Pin NO. Back Side Pin NO. Front Side Pin NO.
PAGE 5
1200pin Unbuffered DDR2 SDRAM SO-DIMMs FUNCTIONAL BLOCK DIAGRAM 512MB(64Mbx64): HMP164S6EFR6C 3Ω +/-5% /S1 ODT1 N.C. CKE1 N.C. N.C.
PAGE 6
1200pin Unbuffered DDR2 SDRAM SO-DIMMs FUNCTIONAL BLOCK DIAGRAM 1GB(128Mbx64): HMP112S6EFR6C 3Ω +/-5% ODT1 ODT0 CKE1 CKE0 /S1 /S0 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 3Ω +/-5% BA0-BA2 SDRAMS D0-15 A0-AN SDRAMS D0-15 /RAS SDRAMS D0-15 /CAS SDRAMS D0-15 /WE SDRAMS D0-15 CK0 /CK0 CK1 /CK1 Rev. 0.3 / Dec.
PAGE 7
1200pin Unbuffered DDR2 SDRAM SO-DIMMs FUNCTIONAL BLOCK DIAGRAM 2GB(256Mbx64): HMP125S6EFR8C 3Ω +/-5% CKE1 ODT1 /S1 CKE0 ODT0 /S0 DQS0 /DQS0 DM0 DQ0 DQ1 DQ2 /CS0 ODT0 CKE0 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS1 ODT1 CKE1 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS0 ODT0 CKE0 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS1 ODT1 CKE1 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 /CS0 ODT0 CKE0 DQS /DQS DM I/O 0 I/O 1 I/O 2 I/O 3
PAGE 8
1200pin Unbuffered DDR2 SDRAM SO-DIMMs ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Note Voltage on VDD pin relative to Vss VDD - 1.0 V ~ 2.3 V V 1 Voltage on VDDQ pin relative to Vss VDDQ - 0.5 V ~ 2.3 V V 1 Voltage on VDDL pin relative to Vss VDDL VIN, VOUT -0.5V ~ 2.3 V V 1 - 0.5 V ~ 2.
PAGE 9
1200pin Unbuffered DDR2 SDRAM SO-DIMMs INPUT DC LOGIC LEVEL Parameter Symbol Min Max Unit dc Input logic HIGH VIH(DC) VREF + 0.125 VDDQ + 0.3 V dc Input logic LOW VIL(DC) -0.30 VREF - 0.125 V Note INPUT AC LOGIC LEVEL Parameter DDR2 400/533 Symbol DDR2 667/800 Min Max Min Max Unit AC Input logic HIGH VIH(AC) VREF + 0.250 - VREF + 0.200 - V AC Input logic LOW VIL(AC) - VREF - 0.250 - VREF - 0.200 V AC INPUT TEST CONDITIONS Symbol Condition Value Units Notes 0.
PAGE 10
1200pin Unbuffered DDR2 SDRAM SO-DIMMs Differential Input AC logic Level Symbol Parameter VID (ac) ac differential input voltage VIX (ac) ac differential cross point voltage Min. Max. Units Note 0.5 VDDQ + 0.6 V 1 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2.
PAGE 11
1200pin Unbuffered DDR2 SDRAM SO-DIMMs OUTPUT BUFFER LEVELS OUTPUT AC TEST CONDITIONS Symbol VOTR Parameter Output Timing Measurement Reference Level SSTL_18 Units Notes 0.5 * VDDQ V 1 Notes: 1. The VDDQ of the device under test is referenced. OUTPUT DC CURRENT DRIVE Symbol Parameter IOH(dc) Output Minimum Source DC Current IOL(dc) Output Minimum Sink DC Current SSTl_18 Units Notes - 13.4 mA 1, 3, 4 13.4 mA 2, 3, 4 Notes: 1. VDDQ = 1.7 V; VOUT = 1420 mV.
PAGE 12
00pin Unbuffered DDR2 SDRAM SO-DIMMs PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25°…) 512MB: HMP164S6EFR6C Pin Symbol Min Max Unit CK, CK CCK 12.5 15 pF CKE, ODT,CS CI1 27 30 pF Address, RAS, CAS, WE CI2 25 32 pF DQ, DM, DQS, DQS CIO 6 7.5 pF Symbol Min Max Unit CK, CK CCK 17 20 pF CKE, ODT,CS CI1 22 25 pF Address, RAS, CAS, WE CI2 28.
PAGE 13
1200pin Unbuffered DDR2 SDRAM SO-DIMMs IDD SPECIFICATIONS (TCASE: 0 to 95oC) 512MB, 64M x 64 SO-DIMM: HMP164S6EFR6C Symbol C4 (DDR2 533@CL4) Y5 (DDR2 667@CL5) S5/S6 (DDR2 800@CL5&6) Unit IDD0 340 360 380 mA IDD1 440 460 480 mA IDD2P 40 40 40 mA IDD2Q 108 120 128 mA IDD2N 140 160 180 mA IDD3P(F) 100 100 100 mA IDD3P(S) 48 48 48 mA IDD3N 180 200 220 mA IDD4W 620 800 920 mA IDD4R 620 740 860 mA IDD5B 640 660 680 mA IDD6 40 40 40 mA 1 IDD6(L) 20
PAGE 14
1200pin Unbuffered DDR2 SDRAM SO-DIMMs 2GB, 256M x 64 SO-DIMM: HMP125S6EFR8C Symbol C4 (DDR2 533@CL4) Y5 (DDR2 667@CL5) S5/S6 (DDR2 800@CL5&6) Unit IDD0 800 880 960 mA IDD1 880 960 1040 mA IDD2P 160 160 160 mA IDD2Q 432 480 512 mA IDD2N 560 640 720 mA IDD3P(F) 400 400 400 mA IDD3P(S) 192 192 192 mA IDD3N 720 800 880 mA IDD4W 1240 1480 1720 mA IDD4R 1240 1440 1640 mA IDD5B 1560 1640 1720 mA IDD6 160 160 160 mA 1 IDD6(L) 80 80 80 mA 1 IDD
PAGE 15
1200pin Unbuffered DDR2 SDRAM SO-DIMMs IDD Measurement Conditions Symbol Conditions Units IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin (IDD);CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD1 Operating one bank active-read-precharge current; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin (IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH betw
PAGE 16
1200pin Unbuffered DDR2 SDRAM SO-DIMMs Electrical Characteristics & AC Timings Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin Speed DDR2-800 (S5) DDR2-800 (S6) DDR2-667 (Y5) DDR2-533 (C4) Unit Bin (CL-tRCD-tRP) 5-5-5 6-6-6 5-5-5 4-4-4 Parameter min min min min CAS Latency 5 6 5 4 tCK tRCD 12.5 15 15 15 ns tRP 12.5 15 15 15 ns tRAS 45 45 45 45 ns tRC 57.
PAGE 17
1200pin Unbuffered DDR2 SDRAM SO-DIMMs - Continued Parameter Symbol Address and control input hold time Read preamble Read postamble Auto-Refresh to Active/Auto-Refresh command period Row Active to Row Active Delay for 1KB page size DDR2-400 DDR2-533 Unit Note Min Max Min Max tIH tRPRE tRPST 475 0.9 0.4 1.1 0.6 375 0.9 0.4 1.1 0.6 ps tCK tCK tRFC 127.5 - 127.5 - ns tRRD 7.5 - 7.
PAGE 18
1200pin Unbuffered DDR2 SDRAM SO-DIMMs Parameter DQ output access time from CK/CK DDR2-667 Symbol DDR2-800 Unit min max min max Note tAC -450 +450 -400 +400 tDQSCK -400 +400 -350 +350 ps CK high-level width tCH 0.45 0.55 0.48 0.52 tCK CK low-level width tCL 0.45 0.55 0.48 0.
PAGE 19
1200pin Unbuffered DDR2 SDRAM SO-DIMMs - continued Parameter Symbol DDR2-667 min DDR2-800 max Unit Note min max 2 - tCK CAS to CAS command delay tCCD 2 Write recovery time tWR 15 - 15 - ns Auto precharge write recovery + precharge time tDAL WR+tRP - WR+tRP - tCK Internal write to read command delay tWTR 7.5 - 7.5 - ns Internal read to precharge command delay tRTP 7.5 7.
PAGE 20
1200pin Unbuffered DDR2 SDRAM SO-DIMMs PACKAGE OUTLINE 64Mx64 - HMP164S6EFR6C Front 67.60 2.00 Min Detail B PIN 1 PIN 39 20.00 30.00 4.00 ± 0.10 Detail A PIN 199 PIN 41 11.40 1.80 ± 0.10 47.40 6.00 2.15 4.20 11.40 2.45 Detail B SIDE Back 3.8MAX 47.40 1.50 ± 0.10 PIN 2 PIN 40 PIN42 PIN 200 1.00 ± 0.10 Detail of Contacts B (Front) Detail of Contacts A Detail of Contacts B (Back) 0.45 ± 0.03 0.60 4.20 4.0 ± 0.10 1.50 2.55 0.20 ± 0.15 2.70 ± 0.10 1.0 ± 0.05 4.20 2.40 ± 0.
PAGE 21
1200pin Unbuffered DDR2 SDRAM SO-DIMMs PACKAGE OUTLINE 128Mx64 - HMP112S6EFR6C Front 67.60 2.00 Min Detail B PIN 1 PIN 39 20.00 30.00 4.00 ± 0.10 Detail A PIN 199 PIN 41 11.40 1.80 ± 0.10 47.40 4.20 SIDE Back 11.40 2.45 6.00 2.15 3.8MAX 47.40 1.50 ± 0.10 PIN 2 PIN 40 PIN42 PIN 200 Detail B 1.00 ± 0.10 Detail of Contacts B (Front) Detail of Contacts A 0.60 0.45 ± 0.03 4.20 4.0 ± 0.10 1.50 2.55 0.20 ± 0.15 2.70 ± 0.10 Detail of Contacts B (Back) 1.0 ± 0.05 2.40 ± 0.10 1.
PAGE 22
1200pin Unbuffered DDR2 SDRAM SO-DIMMs PACKAGE OUTLINE 256Mx64 - HMP125S6EFR8C Front 67.60 2.00 Min Detail B PIN 39 PIN 1 20.00 30.00 4.00 ± 0.10 Detail A PIN 199 PIN 41 11.40 1.80 ± 0.10 47.40 4.20 11.40 2.45 Detail B 6.00 2.15 SIDE Back 47.40 3.8MAX 1.50 ± 0.10 PIN 2 PIN 40 PIN 200 PIN42 1.00 ± 0.10 Detail of Contacts B (Front) Detail of Contacts A Detail of Contacts B (Back) 0.45 ± 0.03 0.60 4.20 4.0 ± 0.10 1.50 2.55 0.20 ± 0.15 2.70 ± 0.10 1.0 ± 0.05 2.40 ± 0.10 1.
PAGE 23
1200pin Unbuffered DDR2 SDRAM SO-DIMMs REVISION HISTORY Revision History Date 0.1 Initial data sheet released Jun. 2008 0.2 Editorial Correction Sep. 2008 0.3 Udated AC Timing Parameters by Speed Grade Dec. 2009 Rev. 0.3 / Dec.