7 Series FPGAs SelectIO Resources User Guide UG471 (v1.
The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products.
Date Version Revision 07/20/2012 1.2 (Cont’d) Updated ILOGIC Resources. In Table 2-3, added TICOCKD/TIOCKDD and removed TICE1Q. Updated Input Delay Resources (IDELAY). Updated functional description of LD port in Table 2-4. In IDELAY Ports, updated Module Load - LD and Increment/Decrement Signals - CE, INC, and added Pipeline Register Load LDPIPEEN and Pipeline Register Reset - REGRST. Removed Table 2-5: “Control Pin Descriptions.” Updated descriptions of IDELAY_TYPE and IDELAY_VALUE in Table 2-5.
Date Version Revision 05/13/2014 1.4 (Cont’d) Added to list of criteria after Table 1-44. Added note to Table 1-48. Updated description after Table 1-51. Updated VCCO Input column in Table 1-55. Added note 3 to Table 1-56. Updated DLYIN connection in Figure 2-4. Updated Clock Input - C, page 116. Updated description of PIPE_SEL in Table 2-5 and Table 2-14. Added VAR_LOAD description to first paragraph of Stability after an Increment/Decrement Operation, page 122. Removed center I/Os from Figure 2-16.
Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter 1: SelectIO Resources I/O Tile Overview . .
IOBUFDS_DIFF_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOBUFDS_DIFF_OUT_DCIEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOBUFDS_DIFF_OUT_INTERMDISABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOBUFDS_INTERMDISABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSTL18, SSTL15, SSTL135, SSTL12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential SSTL18, SSTL15, SSTL135, SSTL12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSTL18, SSTL15, SSTL135, or SSTL12 (T_DCI) Termination . . . . . . . . . . . . . . . . . . . . . HSUL_12 (High Speed Unterminated Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HSUL_12 and DIFF_HSUL_12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Combinatorial Output Data and 3-State Control Path . . . . . . . . . . . . . . . . . . . . . . . . . Output DDR Overview (ODDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPPOSITE_EDGE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAME_EDGE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Forwarding . . . . . . . . . . . . . . . . . . . . . . . . .
ISERDESE2 Feedback from OSERDESE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using D and DDLY in the ISERDESE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISERDESE2 Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISERDESE2 VHDL and Verilog Instantiation Template . . . . . . . . . .
Send Feedback www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide UG471 (v1.
Preface About This Guide Xilinx® 7 series FPGAs include three unified FPGA families that are all designed for lowest power to enable a common design to scale across families for optimal power, performance, and cost. The Artix™-7 family is optimized for lowest cost and absolute power for the highest volume applications. The Virtex®-7 family is optimized for highest system performance and capacity. The Kintex™-7 family is an innovative class of FPGAs optimized for the best price-performance.
Preface: About This Guide 12 Send Feedback www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide UG471 (v1.
Chapter 1 SelectIO Resources I/O Tile Overview Input/output characteristics and logic resources are covered in three consecutive chapters. Chapter 1, SelectIO Resources describes the electrical behavior of the output drivers and input receivers, and gives detailed examples of many standard interfaces. Chapter 2, SelectIO Logic Resources describes the input and output data registers and their double-data rate (DDR) operation, and the programmable input delay (IDELAY) and programmable output delay (ODELAY).
Chapter 1: SelectIO Resources Table 1-1: Supported Features in the HR and HP I/O Banks (Cont’d) Feature HP I/O Banks HR I/O Banks Internal differential termination (DIFF_TERM) Supported Supported IDELAY Supported Supported ODELAY Supported N/A IDELAYCTRL Supported Supported ISERDES Supported Supported OSERDES Supported Supported N/A Supported ZHOLD_DELAY Notes: 1. Not all I/O standards and drive strengths are supported in both the HP and HR I/O banks.
SelectIO Resources Introduction SelectIO Resources Introduction All 7 series FPGAs have configurable SelectIO drivers and receivers, supporting a wide variety of standard interfaces. The robust feature set includes programmable control of output strength and slew rate, on-chip termination using digitally-controlled impedance (DCI), and the ability to internally generate a reference voltage (INTERNAL_VREF). Note: HR banks do not have DCI.
Chapter 1: SelectIO Resources X-Ref Target - Figure 1-2 PAD T PADOUT O I DCITERMDISABLE DIFFI_IN DIFFO_OUT IBUFDISABLE O_OUT UG471_c1_04_010711 Figure 1-2: Regular HP IOB Diagram X-Ref Target - Figure 1-3 PAD T PADOUT O I DIFFI_IN IBUFDISABLE UG471_c1_05 _011010 Figure 1-3: Single-Ended (Only) HR IOB Diagram X-Ref Target - Figure 1-4 PAD T PADOUT O I DIFFI_IN DIFFO_OUT IBUFDISABLE O_OUT UG471_c1_06_011110 Figure 1-4: 16 Send Feedback Regular HR IOB Diagram www.xilinx.
SelectIO Resources General Guidelines SelectIO Resources General Guidelines This section summarizes the general guidelines to be considered when designing with the SelectIO resources in 7 series FPGAs. 7 Series FPGA I/O Bank Rules In 7 series devices, an I/O bank consists of 50 IOBs. The number of banks depends upon the device size and the package pinout. In the 7 Series FPGAs Overview the total number of available I/O banks is listed by device type. For example, the XC7K325T has 10 usable I/O banks.
Chapter 1: SelectIO Resources Supply Voltages for the SelectIO Pins VCCO The VCCO supply is the primary power supply of the 7 series I/O circuitry. The VCCO (V) columns in Table 1-55 provide the VCCO requirements for each of the supported I/O standards, and illustrate the VCCO requirements for both inputs and outputs as well as the optional internal differential termination circuit.
7 Series FPGA DCI—Only available in the HP I/O banks There is a design constraint for I/O nets and primitives called VCCAUX_IO, which should be specified in the design if the VCCAUX_IO pins for any banks are to be set at 2.0V. See 7 Series FPGA SelectIO Attributes/Constraints, page 46 for information on this constraint. The VCCAUX_IO pins are connected together internally inside Kintex-7 and Virtex-7 device packages in groups of three or four HP I/O banks.
Chapter 1: SelectIO Resources impedance due to process variation. It also continuously adjusts the impedances to compensate for variations of temperature and supply voltage fluctuations. For the I/O standards with controlled impedance drivers, DCI controls the driver impedance to either match the two reference resistors, or for some standards, to match half the value of these reference resistors.
7 Series FPGA DCI—Only available in the HP I/O banks For controlled impedance output drivers, the impedance can be adjusted either to match the reference resistors or half the resistance of the reference resistors. For on-chip termination, the termination is always adjusted to match the reference resistors.
Chapter 1: SelectIO Resources DCIRESET Primitive DCIRESET is a Xilinx design primitive that provides the capability to perform a reset of the DCI controller state machine during normal operation of the design. Unless DCIUpdateMode is set to Quiet (see DCIUpdateMode Configuration Option) or for the case outlined below related to the use of multi-function pins set to use DCI, for most situations this primitive should not be required in a design.
7 Series FPGA DCI—Only available in the HP I/O banks Figure 1-7 shows DCI cascading support over multiple I/O banks. Bank B is the master I/O bank, and Banks A and C are considered slave I/O banks. X-Ref Target - Figure 1-7 To Banks Above (When Cascaded) To Local Bank Bank A To Local Bank DCI To Local Bank VRN/VRP Bank B Bank C To Banks Below (When Cascaded) Figure 1-7: 7 Series FPGAs SelectIO Resources User Guide UG471 (v1.
Chapter 1: SelectIO Resources The guidelines when using DCI cascading are as follows: 24 • DCI cascading is only available through a column of HP I/O banks • The master and slave SelectIO banks must all reside on the same HP I/O column on the device and can span the entire column unless there is an interposer boundary. • DCI cascading cannot pass through the interposer boundaries of the larger Virtex-7 devices with stacked silicon interconnect (SSI) technology.
7 Series FPGA DCI—Only available in the HP I/O banks Controlled Impedance Driver (Source Termination) To optimize signal integrity for high-speed or high-performance applications, extra measures are required to match the output impedance of drivers to the impedance of the transmission lines and receivers. Optimally, drivers must have an output impedance matching the characteristic impedance of the driven line, otherwise reflections can occur due to discontinuities.
Chapter 1: SelectIO Resources Split-Termination DCI (Thevenin Equivalent Termination to VCCO/2) Some I/O standards (e.g., HSTL and SSTL) require an input termination resistance (R) to a VTT voltage of VCCO/2 (see Figure 1-10). X-Ref Target - Figure 1-10 VCCO/2 IOB R Z0 VREF 7 Series FPGA UG471_c1_12_011811 Figure 1-10: Input Termination to VCCO /2 without DCI Split-termination DCI creates a Thevenin equivalent circuit using two resistors of twice the resistance value (2R).
7 Series FPGA DCI—Only available in the HP I/O banks Figure 1-11 illustrates split-termination DCI inside a 7 series device.
Chapter 1: SelectIO Resources DCI and 3-state DCI (T_DCI) The class-I driver versions of the SSTL and HSTL I/O standards are only supported for unidirectional signaling; they can only be assigned to input-only or output-only pins in a design, not bidirectional pins. The DCI versions of class-I SSTL and HSTL I/O standards only have internal split-termination resistors present on inputs (not outputs).
7 Series FPGA DCI—Only available in the HP I/O banks The I/O standards with split-termination DCI resistors that are always present are shown in Table 1-3.
Chapter 1: SelectIO Resources To correctly use DCI in 7 series devices: 1. VCCO pins must be connected to the appropriate VCCO voltage based on the IOSTANDARDs in that I/O bank. 2. Correct DCI I/O buffers must be used in the software either by using IOSTANDARD attributes or instantiations in the HDL code. 3. DCI standards require connecting external reference resistors to the multipurpose pins (VRN and VRP).
7 Series FPGA DCI—Only available in the HP I/O banks DCI Usage Examples • Figure 1-13 provides examples illustrating the use of the HSTL_I_DCI and HSTL_II_DCI I/O standards. • Figure 1-14 provides examples illustrating the use of the SSTL18_I_DCI and SSTL18_II_DCI I/O standards.
Chapter 1: SelectIO Resources X-Ref Target - Figure 1-14 SSTL18_I SSTL18_II VCCO/2 VCCO/2 R Conventional Z0 R Z0 VCCO/2 DCI Transmit Conventional Receive VCCO/2 R R VCCO VCCO/2 2R R Z0 Z0 2R 7 Series FPGA HP Bank DCI 7 Series FPGA HP Bank DCI VCCO VCCO/2 2R Conventional Transmit DCI Receive VCCO 2R R Z0 Z0 2R 2R 7 Series FPGA HP Bank DCI 7 Series FPGA HP Bank DCI VCCO 2R DCI Transmit DCI Receive VCCO VCCO 2R 2R Z0 Z0 2R 7 Series FPGA HP Bank DCI 2R 2R 7 Series FPGA
Uncalibrated Split Termination in High-Range I/O Banks (IN_TERM) Uncalibrated Split Termination in High-Range I/O Banks (IN_TERM) The HR I/O banks have an optional on-chip split-termination feature very similar to the 3-state split-termination DCI feature available in the HP I/O banks. Similar to the 3-state split-termination DCI in the HP banks, the option in the HR banks creates a Thevenin equivalent circuit using two internal resistors of twice the target resistance value.
Chapter 1: SelectIO Resources 7 Series FPGA SelectIO Primitives The Xilinx software library includes an extensive list of primitives to support a variety of I/O standards available in the 7 series FPGA I/O primitives. The following generic primitives can each support most of the available single-ended I/O standards.
7 Series FPGA SelectIO Primitives More information including instantiation techniques and available attributes for these and all other design primitives is available in UG768: Xilinx 7 Series FPGA Libraries Guide for HDL Designs. IBUF and IBUFG Signals used as inputs to 7 series devices must use an input buffer (IBUF). The generic 7 series FPGA IBUF primitive is shown in Figure 1-15.
Chapter 1: SelectIO Resources IBUF_INTERMDISABLE The IBUF_INTERMDISABLE primitive shown in Figure 1-17 is available in the HR I/O banks and is similar to the IBUF_IBUFDISABLE primitive in that it has a IBUFDISABLE port that can be used to disable the input buffer during periods that the buffer is not being used. The IBUF_INTERMDISABLE primitive also has an INTERMDISABLE port that can be used to disable the optional uncalibrated split-termination feature.
7 Series FPGA SelectIO Primitives IBUFDS_DIFF_OUT and IBUFGDS_DIFF_OUT Figure 1-19 shows the differential input buffer primitives with complementary outputs (O and OB). IBUFDS_DIFF_OUT and IBUFGDS_DIFF_OUT primitives are the same, IBUFGDS_DIFF_OUT is used for clock inputs. These primitives are only recommended for use by experienced Xilinx designers.
Chapter 1: SelectIO Resources X-Ref Target - Figure 1-21 IBUFDS_IBUFDISABLE IBUFDISABLE I O IB UG471_c1_65_041412 Figure 1-21: Differential Input Buffer With Input Buffer Disable (IBUFDS_IBUFDISABLE) The IBUFDS_IBUFDISABLE primitive can disable the input buffer and force the O output to the fabric to a logic High when the USE_IBUFDISABLE attribute is set to TRUE and the IBUFDISABLE signal is asserted High. If USE_IBUFDISABLE is set to FALSE, this input is ignored and should be tied to ground.
7 Series FPGA SelectIO Primitives IBUFDISABLE port that can be used to disable the input buffer during periods that the buffer is not being used. The IBUFDS_DIFF_OUT_INTERMDISABLE primitive also has an INTERMDISABLE port that can be used to disable the optional uncalibrated split-termination feature. See Uncalibrated Split Termination in High-Range I/O Banks (IN_TERM) for more details on this feature.
Chapter 1: SelectIO Resources Split-Termination DCI (Thevenin Equivalent Termination to VCCO/2) and DCI and 3-state DCI (T_DCI) for more details.
7 Series FPGA SelectIO Primitives The IOBUF_INTERMDISABLE primitive can disable the input buffer and force the O output to the fabric to a logic High when the USE_IBUFDISABLE attribute is set to TRUE and the IBUFDISABLE signal is asserted High. If USE_IBUFDISABLE is set to FALSE, this input is ignored and should be tied to ground. If the I/O is using the optional uncalibrated split-termination feature (IN_TERM), those termination legs are disabled whenever the driver is active (T is low).
Chapter 1: SelectIO Resources X-Ref Target - Figure 1-28 IOBUFDS_DCIEN T I IO IOB O IBUFDISABLE DCITERMDISABLE UG471_c1_69_021214 Figure 1-28: Differential Bidirectional Buffer With Input Path Disable and DCI Disable (IOBUFDS_DCIEN) The IOBUFDS_DCIEN primitive can disable the input buffer and force the O output to the fabric to a logic High when the USE_IBUFDISABLE attribute is set to TRUE and the IBUFDISABLE signal is asserted High.
7 Series FPGA SelectIO Primitives X-Ref Target - Figure 1-29 IOBUFDS_DIFF_OUT 3-state input from TM master OLOGIC I Input from FPGA IO O Output to FPGA To/From Device Pad OB IOB 3-state input from TS slave OLOGIC Figure 1-29: ug471_c1_26_041112 Differential Input/Output Buffer Primitive With Complementary Outputs for the Input Buffer (IOBUFDS_DIFF_OUT) IOBUFDS_DIFF_OUT_DCIEN The IOBUFDS_DIFF_OUT_DCIEN primitive shown in Figure 1-30 is available in the HP I/O banks.
Chapter 1: SelectIO Resources split-termination DCI feature, this primitive disables the termination legs whenever the DCITERMDISABLE signal is asserted high. Only the 3-state DCI I/O standards can be used on bidirectional signals. With 3-state DCI I/O standards, the DCI termination legs turn off whenever the driver is active (TS is low for the IO output, TM is low for the IOB output).
7 Series FPGA SelectIO Primitives (IN_TERM) for more details on this feature.
Chapter 1: SelectIO Resources X-Ref Target - Figure 1-34 OBUFDS I Input from FPGA + O – OB Output to Device Pads ug471_c1_22_041112 Figure 1-34: Differential Output Buffer Primitive (OBUFDS) OBUFT The generic 3-state output buffer OBUFT, shown in Figure 1-35, typically implements 3-state outputs or bidirectional I/O.
7 Series FPGA SelectIO Attributes/Constraints CONFIG DCI_CASCADE = " ..."; For example: CONFIG DCI_CASCADE = "11 13 15 17"; Location Constraints The location constraint (LOC) must be used to specify the I/O location of an instantiated I/O primitive. The possible values for the location constraint are all the external port identifiers (e.g., A8, M5, AM6, etc.). These values are device and package size dependent.
Chapter 1: SelectIO Resources • All VREF-based inputs such as HSLVDCI, SSTL, HSTL, and HSUL • All input and bidirectional primitives The IBUF_LOW_PWR attribute allows an optional trade-off between performance and power. The change in the performance is reflected in the delay through the input buffer and can be measured in the static timing report for the design. The change in power can be estimated using the XPower Estimator (XPE) or XPower Analyzer (XPA) tools.
7 Series FPGA SelectIO Attributes/Constraints The DRIVE attribute uses the following syntax in the UCF file: INST DRIVE = ""; PULLUP/PULLDOWN/KEEPER Attribute for IBUF, OBUFT, and IOBUF Input buffers (e.g., IBUF), 3-state output (e.g., OBUFT), and bidirectional (e.g., IOBUF) buffers can have a weak pull-up resistor, a weak pull-down resistor, or a weak “keeper” circuit.
Chapter 1: SelectIO Resources Internal VREF The VREF for an I/O bank can be (optionally) generated inside the 7 series FPGA. Internal generation removes the need to provide for a particular VREF supply rail on the printed circuit board (PCB) and frees the multi-purpose VREF pins in a given I/O bank to be used as normal I/O pins.
Supported I/O Standards and Terminations In Verilog, the Verilog constraint is placed immediately before the module or instantiation of the IOB primitive.
Chapter 1: SelectIO Resources Figure 1-37 shows unidirectional terminated topologies. X-Ref Target - Figure 1-37 IOB IOB LVTTL LVTTL Z0 IOB IOB LVTTL LVTTL RS = Z0 – RD Z0 VTT IOB LVTTL RP = Z0 IOB LVTTL Z0 Note: VTT is any voltage from 0V to VCCO ug471_c1_27_011811 Figure 1-37: 52 Send Feedback LVTTL Unidirectional Termination www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide UG471 (v1.
Supported I/O Standards and Terminations Figure 1-38 shows a bidirectional, parallel-terminated topology. X-Ref Target - Figure 1-38 IOB IOB LVTTL LVTTL Z0 IOB VTT VTT LVTTL IOB LVTTL RP = Z0 RP = Z0 Z0 Note: VTT is any voltage from 0V to VCCO ug471_c1_28_011811 Figure 1-38: LVTTL Bidirectional Termination Table 1-10 details the allowed attributes that can be applied to the LVTTL I/O standard. This standard is only available in the HR I/O banks.
Chapter 1: SelectIO Resources LVCMOS (Low Voltage CMOS) Table 1-11: Available I/O Bank Type HR HP Available Available LVCMOS is a widely used switching standard implemented in CMOS transistors. This standard is defined by JEDEC (JESD 8C.01). The LVCMOS standards supported in 7 series FPGAs are: LVCMOS12, LVCMOS15, LVCMOS18, LVCMOS25, and LVCMOS33. Sample circuits illustrating both unidirectional and bidirectional LVCMOS termination techniques are shown in Figure 1-39 and Figure 1-40.
Supported I/O Standards and Terminations Figure 1-40 shows a bidirectional, parallel-terminated topology. X-Ref Target - Figure 1-40 IOB IOB LVCMOS LVCMOS Z0 VTT VTT IOB LVCMOS IOB LVCMOS RP = Z0 RP = Z0 Z0 Note: VTT is any voltage from 0V to VCCO ug471_c1_30_011811 Figure 1-40: LVCMOS Bidirectional Termination Table 1-12 details the allowed attributes that can be applied to the LVCMOS33 and LVCMOS25 I/O standards. These standards are only available in the HR I/O banks.
Chapter 1: SelectIO Resources Table 1-14 details the allowed attributes that can be applied to the LVCMOS15 I/O standard. This standard is available in both the HR and HP I/O banks.
Supported I/O Standards and Terminations X-Ref Target - Figure 1-41 IOB IOB LVDCI LVDCI Z0 R0 = RVRN = RVRP = Z0 ug471_c1_31_011811 Figure 1-41: Unidirectional Controlled Impedance Driver Topology X-Ref Target - Figure 1-42 IOB IOB LVDCI LVDCI Z0 R0 = RVRN = RVRP = Z0 R0 = RVRN = RVRP = Z0 ug471_c1_32_011811 Figure 1-42: Bidirectional Controlled Impedance Driver Topology LVDCI_DV2 Table 1-17: Available I/O Bank Type HR HP N/A Available A controlled impedance driver with half impedan
Chapter 1: SelectIO Resources X-Ref Target - Figure 1-43 IOB IOB LVDCI_DV2 LVDCI_DV2 Z0 R0 = ½RVRN = ½RVRP = Z0 ug471_c1_33_011811 Figure 1-43: Unidirectional Controlled Impedance Driver with Half Impedance Topology X-Ref Target - Figure 1-44 IOB IOB LVDCI_DV2 LVDCI_DV2 Z0 R0 = ½RVRN = ½RVRP = Z0 R0 = ½RVRN = ½RVRP = Z0 ug471_c1_34_011811 Figure 1-44: Bidirectional Controlled Impedance Driver with Half Impedance Topology There are no optional current drive strength settings for LVDCI drive
Supported I/O Standards and Terminations HSLVDCI (High-Speed LVDCI) Table 1-18: Available I/O Bank Type HR HP N/A Available The HSLVDCI standard is intended for bidirectional use. The driver is identical to LVDCI, while the input is identical to HSTL and SSTL. By using a VREF-referenced input, HSLVDCI allows greater input sensitivity at the receiver than when using a single-ended LVCMOS-type receiver.
Chapter 1: SelectIO Resources HSTL (High-Speed Transceiver Logic) The high-speed transceiver logic (HSTL) standard is a general purpose high-speed bus standard is defined by JEDEC (JESD8-6). The HSTL standards have four variations (classes). To support clocking high-speed memory interfaces, differential versions are also available. 7 series FPGA I/O supports class-I for the 1.2V version of HSTL (in HP banks), and class-I and II for the 1.5V and 1.8V versions, including the differential versions.
Supported I/O Standards and Terminations HSTL_ II_DCI and HSTL_ II_DCI_18 Table 1-23: Available I/O Bank Type HR HP N/A Available HSTL_II_DCI and HSTL_II_DCI_18 provide on-chip split thevenin termination powered from VCCO, creating an equivalent termination voltage of VCCO/2, and are intended for use in bidirectional links.
Chapter 1: SelectIO Resources Differential HSTL can also be used for differential clock and DQS signals in memory interface designs. DIFF_HSTL_II_DCI and DIFF_HSTL_II_DCI_18 Table 1-28: Available I/O Bank Type HR HP N/A Available Differential HSTL class-II pairs complementary single-ended HSTL_II type drivers with a differential receiver, including on-chip split-thevenin termination. Differential HSTL class-II is intended to be used in bidirectional links.
Supported I/O Standards and Terminations X-Ref Target - Figure 1-46 External Termination VTT = 0.75V for HSTL_I 0.6V for HSTL_I_12 0.9V for HSTL_I_18 IOB HSTL_I HSTL_I_12 HSTL_I_18 IOB HSTL_I HSTL_I_12 HSTL_I_18 RP = Z0 = 50Ω + Z0 VREF = 0.75V for HSTL_I 0.6V for HSTL_I_12 0.9V for HSTL_I_18 – DCI IOB IOB VCCO = 1.5V for HSTL_I_DCI 1.8V for HSTL_I_DCI_18 RVRN = 2Z0= 100Ω HSTL_I_DCI HSTL_I_DCI_18 HSTL_I_DCI HSTL_I_DCI_18 + Z0 VREF = 0.75V for HSTL_I_DCI 0.
Chapter 1: SelectIO Resources Differential HSTL Class I Figure 1-47 shows a sample circuit illustrating a termination technique for differential HSTL class-I (1.5V or 1.8V) with unidirectional termination. In a specific circuit, all drivers and receivers must be at the same voltage level (either 1.5V or 1.8V); they are not interchangeable. X-Ref Target - Figure 1-47 External Termination VTT = 0.75V for HSTL_I 0.
Supported I/O Standards and Terminations Figure 1-48 shows a sample circuit illustrating a termination technique for differential HSTL class-I (1.5V or 1.8V) with unidirectional DCI termination. In a specific circuit, all drivers and receivers must be at the same voltage level (either 1.5V or 1.8V); they are not interchangeable. Only HP I/O banks support these DCI standards. X-Ref Target - Figure 1-48 DCI IOB IOB VCCO = 1.5V for DIFF_HSTL_I_DCI 1.
Chapter 1: SelectIO Resources HSTL Class II Figure 1-49 shows a sample circuit illustrating a termination technique for HSTL class-II (1.5V or 1.8V) with unidirectional termination. In a specific circuit, all drivers and receivers must be at the same voltage level (either 1.5V or 1.8V); they are not interchangeable. Only HP I/O banks support the DCI standards. The internal split-termination resistors are always present, independent of whether the drivers are 3-stated.
Supported I/O Standards and Terminations Figure 1-50 shows a sample circuit illustrating a termination technique for HSTL class-II (1.5V or 1.8V) with bidirectional termination. In a specific circuit, all drivers and receivers must be at the same voltage level (either 1.5V or 1.8V); they are not interchangeable. Only HP I/O banks support the DCI standards. The internal split-termination resistors are always present, independent of whether the drivers are 3-stated.
Chapter 1: SelectIO Resources Differential HSTL Class II Figure 1-51 shows a sample circuit illustrating a termination technique for differential HSTL class-II (1.5V or 1.8V) with unidirectional termination. In a specific circuit, all drivers and receivers must be at the same voltage level (either 1.5V or 1.8V); they are not interchangeable. X-Ref Target - Figure 1-51 External Termination DIFF_HSTL_II DIFF_HSTL_II_18 IOB VTT = 0.75V for DIFF_HSTL_II 0.9V for DIFF_HSTL_II_18 VTT = 0.
Supported I/O Standards and Terminations Figure 1-52 shows a sample circuit illustrating a termination technique for differential HSTL class-II (1.5V or 1.8V) with unidirectional DCI termination. In a specific circuit, all drivers and receivers must be at the same voltage level (either 1.5V or 1.8V); they are not interchangeable. Only HP I/O banks support the DCI standards. Only HP I/O banks support the DCI standards.
Chapter 1: SelectIO Resources Figure 1-53 shows a sample circuit illustrating a termination technique for differential HSTL class-II (1.5V or 1.8V) with bidirectional termination. In a specific circuit, all drivers and receivers must be at the same voltage level (either 1.5V or 1.8V); they are not interchangeable. X-Ref Target - Figure 1-53 VTT = 0.75V for DIFF_HSTL_II 0.9V for DIFF_HSTL_II_18 External Termination IOB DIFF_HSTL_II DIFF_HSTL_II_18 VTT = 0.75V for DIFF_HSTL_II 0.
Supported I/O Standards and Terminations Figure 1-54 shows a sample circuit illustrating a termination technique for differential HSTL class-II (1.5V or 1.8V) with bidirectional DCI termination. In a specific circuit, all drivers and receivers must be at the same voltage level (either 1.5V or 1.8V); they are not interchangeable. Only HP I/O banks support the DCI standards. The internal split-termination resistors are always present, independent of whether the drivers are 3-stated.
Chapter 1: SelectIO Resources HSTL_II_T_DCI (1.5V or 1.8V) Split-Thevenin Termination (3-state) Figure 1-55 shows a sample circuit illustrating a termination technique for HSTL_II_T_DCI (1.5V) and HSTL_II_T_DCI_18 (1.8V) with on-chip split-thevenin termination. In this bidirectional case, when 3-stated, the termination is invoked on the receiver and not on the driver. In a specific circuit, all drivers and receivers must be at the same voltage level (either 1.5V or 1.8V); they are not interchangeable.
Supported I/O Standards and Terminations Figure 1-56 shows a sample circuit illustrating a termination technique for differential HSTL class-II (1.5V or 1.8V) with on-chip split-thevenin termination. In a specific circuit, all drivers and receivers must be at the same voltage level (either 1.5V or 1.8V); they are not interchangeable. Only HP I/O banks support the T_DCI standards. The internal split-termination resistors are only present when the output buffers are 3-stated.
Chapter 1: SelectIO Resources SSTL (Stub-Series Terminated Logic) The Stub-Series Terminated Logic (SSTL) for 1.8V (SSTL18), 1.5V (SSTL15), and 1.35V (SSTL135) are I/O standards used for general purpose memory buses. While example termination techniques are discussed in this section, the optimal termination schemes for a given memory interface are determined using signal-integrity analysis of the actual PCB topology including the memory devices used, the board layout, and transmission line impedances.
Supported I/O Standards and Terminations bidirectional signals (no input-only or output-only). HR banks provide IN_TERM options for untuned internal parallel split-termination resistors. Although the optimal drive and termination scheme for any new design is determined through careful signal-integrity analysis, initial considerations include: • HP I/O banks: SSTL15_T_DCI at the 7 series FPGAs bidirectional pins (DQ and DQS), and SSTL15 at the unidirectional pins (all other pins).
Chapter 1: SelectIO Resources SSTL15_R, SSTL135_R, DIFF_SSTL15_R, DIFF_SSTL135_R Table 1-30: Available I/O Bank Type HR HP Available N/A The reduced drive-strength R standards are versions of the standard drivers, which can be preferred for short, point-to-point board topologies. Parallel end-termination resistors (commonly 50Ω) to VTT = (VCCO/2) are typically placed on the board close to any receiver.
Supported I/O Standards and Terminations Note: A lower resistance value can be used for the parallel end-termination resistors in some DDR3 applications. Refer to UG586: Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions v2.0 User Guide for details.
Chapter 1: SelectIO Resources SSTL18, SSTL15, SSTL135, SSTL12 Figure 1-57 shows a sample circuit illustrating a unidirectional termination technique for SSTL18, SSTL15, SSTL135, or SSTL12. In a specific circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V, 1.35V, or 1.2V); they are not interchangeable. Also shown in Figure 1-57, only SSTL18_II_DCI has internal split-termination resistors present in an output pin. X-Ref Target - Figure 1-57 VTT = 0.9V for SSTL18_(I/II) 0.
Supported I/O Standards and Terminations Figure 1-58 shows a sample circuit illustrating a bidirectional termination technique for SSTL18, SSTL15, SSTL135, or SSTL12. In a specific circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V,1.35V, or 1.2V); they are not interchangeable. SSTL18 class-I is not available for bidirectional signaling. Also, SSTL18_II_DCI is the only available DCI standard available for bidirectional signaling.
Chapter 1: SelectIO Resources Differential SSTL18, SSTL15, SSTL135, SSTL12 Figure 1-59 shows a sample circuit illustrating a termination technique for differential SSTL18, SSTL15, SSTL135, or SSTL12 with unidirectional termination. In a specific circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V,1.35V, or 1.2V); they are not interchangeable. X-Ref Target - Figure 1-59 External Termination DIFF_SSTL18_(I/II) DIFF_SSTL15(_R) DIFF_SSTL135(_R) DIFF_SSTL12 IOB VTT = 0.
Supported I/O Standards and Terminations Figure 1-60 shows a sample circuit illustrating a termination technique for differential SSTL18, SSTL15, SSTL135, or SSTL12 with unidirectional DCI termination. In a specific circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V, 1.35V, or 1.2V); they are not interchangeable. Also shown in Figure 1-60, only SSTL18_II_DCI has internal split-termination resistors present in an output pin.
Chapter 1: SelectIO Resources Figure 1-61 shows a sample circuit illustrating a termination technique for differential SSTL18, SSTL15, SSTL135, or SSTL12 with bidirectional termination. In a specific circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V, 1.35V, or 1.2V); they are not interchangeable. Differential SSTL18 class-I is not available for bidirectional use.
Supported I/O Standards and Terminations Figure 1-62 shows a sample circuit illustrating a termination technique for differential SSTL18 with bidirectional DCI termination. DIFF_SSTL18_II_DCI is the only available DCI standard for bidirectional use signaling. The DCI versions of DIFF_SSTL18_I, DIFF_SSTL15, DIFF_SSTL135, and DIFF_SSTL12 are only available for unidirectional signaling. Use the T_DCI standards for bidirectional signaling of DIFF_SSTL15, DIFF_SSTL135, and DIFF_SSTL12 with DCI termination.
Chapter 1: SelectIO Resources SSTL18, SSTL15, SSTL135, or SSTL12 (T_DCI) Termination Figure 1-63 shows a sample circuit illustrating a termination technique for SSTL18, SSTL15, SSTL135, or SSTL12 (T_DCI) with on-chip split-thevenin termination. In this bidirectional I/O standard, when 3-stated, the internal split-termination is invoked on the receiver and not on the driver. X-Ref Target - Figure 1-63 DCI Not 3-stated (T pin logic Low) 3-stated (T pin logic High) IOB IOB VCCO = 1.
Supported I/O Standards and Terminations HSUL_DCI_12 and DIFF_HSUL_12_DCI Table 1-38: Available I/O Bank Type HR HP N/A Available DCI provides a tuned output impedance driver that matches the output impedance to the reference resistors on the VRP and VRN pins. No split termination resistors are present for either drivers or receivers. The differential (DIFF_) versions use complementary single-ended drivers for outputs and differential receivers for inputs.
Chapter 1: SelectIO Resources Figure 1-65 shows a sample circuit illustrating a bidirectional board topology (with no termination) for HSUL_12. Only HP I/O banks support the DCI version. X-Ref Target - Figure 1-65 External Termination IOB IOB HSUL_12 HSUL_12 + Z0 – VREF = 0.60V VREF = 0.60V DCI IOB IOB HSUL_12_DCI HSUL_12_DCI + Z0 – VREF = 0.60V R0 = 50Ω VREF = 0.
Supported I/O Standards and Terminations Figure 1-67 shows a sample circuit illustrating a board topology (with no termination) for differential HSUL_12 with unidirectional DCI signalling.
Chapter 1: SelectIO Resources Figure 1-69 shows a sample circuit illustrating a board topology (with no termination) for differential HSUL_12 with bidirectional DCI signalling.
Supported I/O Standards and Terminations Table 1-40: IOSTANDARD Attributes for Single-Ended HSTL, SSTL, HSUL, or MOBILE_DDR I/O Standards Primitives Attributes IBUF, IBUFG, OBUF, or OBUFT HP I/O Banks IOSTANDARD HR I/O Banks IOBUF HP I/O Banks HR I/O Banks HSTL_I HSTL_I N/A N/A HSTL_I_12 N/A N/A N/A HSTL_I_18 HSTL_I_18 N/A N/A HSTL_I_DCI N/A N/A N/A HSTL_I_DCI_18 N/A N/A N/A HSTL_II HSTL_II HSTL_II HSTL_II HSTL_II_18 HSTL_II_18 HSTL_II_18 HSTL_II_18 HSTL_II_DCI N/A HST
Chapter 1: SelectIO Resources Table 1-41: IOSTANDARD Attributes for Differential HSTL, SSTL, HSUL, or MOBILE_DDR I/O Standards Primitives Attributes IBUFDS, IBUFGDS, IBUFDS_DIFF_OUT, IBUFGDS_DIFF_OUT, OBUFDS, or OBUFTDS HP I/O Banks HR I/O Banks HP I/O Banks HR I/O Banks DIFF_HSTL_I DIFF_HSTL_I N/A N/A DIFF_HSTL_I_18 DIFF_HSTL_I_18 N/A N/A DIFF_HSTL_I_DCI N/A N/A N/A DIFF_HSTL_I_DCI_18 N/A N/A N/A DIFF_HSTL_II DIFF_HSTL_II DIFF_HSTL_II DIFF_HSTL_II DIFF_HSTL_II_18 DIFF_HSTL_II_1
Supported I/O Standards and Terminations Table 1-42: SLEW Attribute for All Single-Ended and Differential HSTL, SSTL, HSUL, and Mobile_DDR IOSTANDARDs Primitives Attribute IBUF, IBUFG, IBUFDS, IBUFGDS, IBUFDS_DIFF_OUT, or IBUFGDS_DIFF_OUT HP I/O Banks SLEW HR I/O Banks N/A N/A OBUF, OBUFT, OBUFDS, or OBUFTDS, IOBUF, IOBUFDS or IOBUFDS_DIFF_OUT HP I/O Banks HR I/O Banks {FAST, SLOW} {FAST, SLOW} LVDS and LVDS_25 (Low Voltage Differential Signaling) Low-voltage differential signaling (LVDS) is a po
Chapter 1: SelectIO Resources X-Ref Target - Figure 1-70 External Termination IOB IOB LVDS LVDS_25 LVDS LVDS_25 Z0 + RDIFF = 2Z0= 100Ω – Z0 ug471_c1_60_011811 Figure 1-70: LVDS or LVDS_25 Receiver Termination Figure 1-71 is an example of a differential termination for an LVDS or LVDS_25 receiver on a board with 50Ω transmission lines.
Supported I/O Standards and Terminations • The differential signals at the input pins meet the VIDIFF (min) requirements in the corresponding LVDS or LVDS_25 DC specifications tables of the specific device family data sheet. • For HR I/O banks in bidirectional configuration, internal differential termination is always used. One way to accomplish the above criteria is to use an external circuit that both AC-couples and DC-biases the input signals.
Chapter 1: SelectIO Resources RSDS (Reduced Swing Differential Signaling) Table 1-45: Available I/O Bank Type HR HP Available N/A Reduced-swing differential signaling (RSDS) is similar to an LVDS high-speed interface using differential signaling. RSDS has a similar implementation to LVDS_25 in 7 series FPGAs and is only intended for point-to-point applications. RSDS is only available in HR I/O banks and requires a VCCO voltage level of 2.5V. The IOSTANDARD is called RSDS_25.
Supported I/O Standards and Terminations PPDS (Point-to-Point Differential Signaling) Table 1-49: Available I/O Bank Type HR HP Available N/A PPDS is a differential I/O standard for next-generation LCD interface row and column drivers. PPDS inputs require a parallel-termination resistor, either through the use of a discrete resistor on the PCB, or by using the 7 series FPGAs DIFF_TERM attribute to enable internal termination.
Chapter 1: SelectIO Resources BLVDS (Bus LVDS) Table 1-53: Available I/O Bank Type HR HP Available N/A Since LVDS is intended for point-to-point applications, BLVDS is not an EIA/TIA standard implementation and requires careful adaptation of I/O and PCB layout design rules. The primitive supplied in the software library for bidirectional LVDS does not use the 7 series FPGA LVDS current-mode driver, instead, it uses complementary single-ended differential drivers.
Rules for Combining I/O Standards in the Same Bank Rules for Combining I/O Standards in the Same Bank The following rules must be obeyed to combine different input, output, and bidirectional standards in the same bank: 1. Combining output standards only. Output standards with the same output VCCO requirement can be combined in the same bank. Compatible example: SSTL15_I and LVDCI_15 outputs Incompatible example: SSTL15 (output VCCO = 1.5V) and LVCMOS18 (output VCCO = 1.8V) outputs 2.
Chapter 1: SelectIO Resources Table 1-55, summarizes the VCCO and VREF requirements for each 7 series FPGA supported I/O standard. For more detailed DC specifications, including the recommended operating ranges of the supplies for each supported I/O standard, see the 7 series FPGA data sheets. Table 1-55: VCCO and VREF Requirements for Each Supported I/O Standard VCCO (V) VREF (V) I/O Bank Availability Output Input Input with DIFF_TERM = TRUE Input BLVDS_25 HR 2.5 2.
Rules for Combining I/O Standards in the Same Bank Table 1-55: VCCO and VREF Requirements for Each Supported I/O Standard (Cont’d) VCCO (V) VREF (V) I/O Bank Availability Output Input Input with DIFF_TERM = TRUE Input DIFF_SSTL18_II_DCI HP 1.8 1.8 N/A N/A DIFF_SSTL18_II_T_DCI HP 1.8 1.8 N/A N/A HSLVDCI_15 HP 1.5 Any N/A 0.75 HSLVDCI_18 HP 1.8 Any N/A 0.9 Both 1.5 Any N/A 0.75 HSTL_I_12 HP 1.2 Any N/A 0.6 HSTL_I_18 Both 1.8 Any N/A 0.9 HSTL_I_DCI HP 1.5 1.
Chapter 1: SelectIO Resources Table 1-55: VCCO and VREF Requirements for Each Supported I/O Standard (Cont’d) I/O Standard VCCO (V) VREF (V) I/O Bank Availability Output Input Input with DIFF_TERM = TRUE Input HR 3.3 3.3 N/A N/A 2.5(1) 2.5 N/A LVTTL (2) MINI_LVDS_25 HR 2.5 MOBILE_DDR HR 1.8 1.8 N/A N/A PCI33_3 HR 3.3 3.3 N/A N/A (2) 2.5(1) 2.5 N/A PPDS_25 HR 2.5 RSDS_25 HR 2.5(2) 2.5(1) 2.5 N/A SSTL135 Both 1.35 Any N/A 0.675 SSTL135_R HR 1.
Rules for Combining I/O Standards in the Same Bank Table 1-56, summarizes the DRIVE and SLEW attribute options, bidirectional buffer availability, and DCI termination type for each 7 series FPGA supported I/O standard.
Chapter 1: SelectIO Resources Table 1-56: DRIVE and SLEW Attributes, Bidirectional Buffers, and DCI Termination Type (Cont’d) I/O Bank Availability DRIVE (mA) SLEW Outputs HSLVDCI_15 HP HSLVDCI_18 DCI Type(2) Outputs Bidirectional Buffers(1) Outputs Inputs N/A N/A Yes Driver None HP N/A N/A Yes Driver None Both N/A SLOW, FAST No None None HSTL_I_12 HP N/A SLOW, FAST No None None HSTL_I_18 Both N/A SLOW, FAST No None None HSTL_I_DCI HP N/A SLOW, FAST No None
Rules for Combining I/O Standards in the Same Bank Table 1-56: DRIVE and SLEW Attributes, Bidirectional Buffers, and DCI Termination Type (Cont’d) I/O Bank Availability DRIVE (mA) SLEW Outputs MINI_LVDS_25 HR MOBILE_DDR DCI Type(2) Outputs Bidirectional Buffers(1) Outputs Inputs N/A N/A Yes(3) None None HR N/A SLOW, FAST Yes None None PCI33_3 HR N/A N/A Yes None None PPDS_25 HR N/A N/A No None None RSDS_25 HR N/A N/A No None None SSTL135 Both N/A SLOW, FAST
Chapter 1: SelectIO Resources Simultaneous Switching Outputs Due to package inductance, each part/package supports a limited number of simultaneous switching outputs (SSOs), particularly when using fast, high-drive outputs. Fast, high-drive outputs should only be used when required by the application.
Chapter 2 SelectIO Logic Resources Introduction This chapter describes the logic directly behind the I/O drivers and receivers covered in Chapter 1, SelectIO Resources. 7 series FPGAs contain the basic I/O logic resources from previous Xilinx FPGAs.
Chapter 2: SelectIO Logic Resources X-Ref Target - Figure 2-2 IDELAYE2 PAD ILOGICE3/ ISERDESE2 IOB OLOGICE3/ OSERDESE2 UG471_c1_02_012211 Figure 2-2: 7 Series FPGA HR Bank I/O Tile ILOGIC Resources The ILOGIC block is located next to the I/O block (IOB). The ILOGIC block contains the synchronous elements for capturing data as it comes into the FPGA through the IOB. The possibilities for ILOGIC configuration in 7 series devices are the ILOGICE2 (HP I/O banks) and ILOGICE3 (HR I/O banks).
ILOGIC Resources X-Ref Target - Figure 2-3 D O DDLY OFB TFB D CE1 Q1 Q1 Q2 Q2 Latch FF DDR CE CK CKB CLK SR CLKB SR UG471_c2_01_090810 Figure 2-3: 7 Series FPGAs SelectIO Resources User Guide UG471 (v1.5) May 15, 2015 ILOGICE2 Block Diagram www.xilinx.
Chapter 2: SelectIO Logic Resources X-Ref Target - Figure 2-4 D O DDLY DLYFABRIC ZHOLD_DELAY DLVIFF DLYIN OFB TFB D CE1 CE CK Q1 Q1 Q2 Q2 Latch FF DDR CKB CLK SR CLKB SR UG471_c2_02_021914 Figure 2-4: ILOGICE3 Block Diagram ILOGIC can support the following operations: • Edge-triggered D-type flip-flop • IDDR mode (OPPOSITE_EDGE or SAME_EDGE or SAME_EDGE_PIPELINED). See Input DDR Overview (IDDR), page 109 for further discussion on input DDR.
ILOGIC Resources The ILOGIC block registers have a common synchronous or asynchronous set and reset (SR signal). The set/reset input pin, SR forces the storage element into the state specified by the SRVAL attributes. The reset condition predominates over the set condition. The SRVAL attributes can be set individually for each storage element in the ILOGIC block, but the choice of synchronous or asynchronous set/reset (SRTYPE) can not be set individually for each storage element in the ILOGIC block.
Chapter 2: SelectIO Logic Resources X-Ref Target - Figure 2-5 C CE D Q1 D0A D1A D2A D3A D4A D5A D6A D7A D8A D9A D10A D11A D12A D13A D0A Q2 D2A D4A D1A D3A D6A D5A D8A D7A D10A D9A D12A D11A ug471_c2_03_090810 Figure 2-5: Input DDR Timing in OPPOSITE_EDGE Mode SAME_EDGE Mode In the SAME_EDGE mode, the data is presented into the FPGA logic on the same clock edge. This structure is similar to the Virtex-6 FPGA implementation.
ILOGIC Resources X-Ref Target - Figure 2-7 C CE D D0A D1A D2A D3A D4A D5A D6A D7A D8A D9A D10A D11A D12A D13A Q1 D0A D2A D4A D6A D8A D10A Q2 D1A D3A D5A D7A D9A D11A ug471_c2_05_090810 Figure 2-7: Input DDR Timing in SAME_EDGE_PIPELINED Mode Input DDR Resources (IDDR) Figure 2-8 shows the block diagram of the IDDR primitive. Set and Reset are not supported at the same time. Table 2-1 lists the IDDR port signals.
Chapter 2: SelectIO Logic Resources Table 2-2: IDDR Attributes Attribute Name Description Possible Values DDR_CLK_EDGE Sets the IDDR mode of operation with respect to clock edge OPPOSITE_EDGE (default), SAME_EDGE, SAME_EDGE_PIPELINED INIT_Q1 Sets the initial value for Q1 port 0 (default), 1 INIT_Q2 Sets the initial value for Q2 port 0 (default), 1 SRTYPE Set/Reset type with respect to clock (C) ASYNC (default), SYNC IDDR VHDL and Verilog Templates The Libraries Guide includes templates for
ILOGIC Resources • At time TIDOCK before Clock Event 1, the input signal becomes valid-high at the D input of the input register and is reflected on the Q1 output of the input register at time TICKQ after Clock Event 1. Clock Event 4 • At time TISRCK before Clock Event 4, the SR signal (configured as synchronous reset in this case) becomes valid-high resetting the input register and reflected at the Q1 output of the IOB at time TICKQ after Clock Event 4.
Chapter 2: SelectIO Logic Resources Clock Event 9 • At time TISRCK before Clock Event 9, the SR signal (configured as synchronous reset in this case) becomes valid-high resetting Q1 at time TICKQ after Clock Event 9, and Q2 at time TICKQ after Clock Event 10. Table 2-3 describes the timing parameters of the ILOGIC switching characteristics in the 7 series FPGA data sheets.
Input Delay Resources (IDELAY) IDELAYE2 Primitive Figure 2-11 shows the IDELAYE2 primitive. X-Ref Target - Figure 2-11 IDELAYE2 C DATAOUT REGRST CNTVALUEOUT[4:0] LD CE INC CINVCTRL CNTVALUEIN[4:0] IDATAIN LDPIPEEN DATAIN ug471_c2_09_011911 Figure 2-11: IDELAYE2 Primitive Table 2-4 lists the available ports in the IDELAYE2 primitive. Table 2-4: IDELAYE2 Primitive Ports Port Name Direction Width Function C Input 1 Clock input used in VARIABLE, VAR_LOAD, or VAR_LOAD_PIPE mode.
Chapter 2: SelectIO Logic Resources IDELAY Ports Data Input from the IOB - IDATAIN The IDATAIN input is driven by its associated IOB. IDELAY can drive data to either an ILOGICE2/ISERDESE2 or ILOGICE3/ISERDESE2 block, directly into the FPGA logic, or to both through the DATAOUT port with a delay set by the IDELAY_VALUE. Data Input from the FPGA Logic - DATAIN The DATAIN input is directly driven by the FPGA logic providing a logic accessible delay line.
Input Delay Resources (IDELAY) Pipeline Register Reset - REGRST When high, this input resets the pipeline register to all zeroes. Increment/Decrement Signals - CE, INC The increment/decrement is controlled by the enable signal (CE). This interface is only available when the IDELAY is in VARIABLE, VAR_LOAD, or VAR_LOAD_PIPE mode. As long as CE remains High, IDELAY will increment or decrement by TIDELAYRESOLUTION every clock (C) cycle.
Chapter 2: SelectIO Logic Resources IDELAY Attributes Table 2-5 summarizes the IDELAY attributes. Table 2-5: IDELAY Attribute Summary Attribute Value Default Value Description Sets the type of tap delay line. FIXED delay sets a static delay value. VAR_LOAD dynamically loads tap values. VARIABLE delay dynamically adjusts the delay value. VAR_LOAD_PIPE is similar to VAR_LOAD mode with the ability to store the CNTVALUEIN value ready for a future update.
Input Delay Resources (IDELAY) IDELAY_TYPE Attribute The IDELAY_TYPE attribute sets the type of delay used. When the IDELAY_TYPE attribute is set to FIXED, the tap-delay value is fixed at the number of taps determined by the IDELAY_VALUE attribute setting. This value is preset and cannot be changed after configuration. When the IDELAY_TYPE attribute is set to VARIABLE, the variable tap delay is selected. The tap delay can be incremented by setting CE = 1 and INC = 1, or decremented by CE = 1 and INC = 0.
Chapter 2: SelectIO Logic Resources IDELAYCTRL primitive must be instantiated. See IDELAYCTRL Usage and Design Guidelines for more details. The control pins being used in VARIABLE mode are described in Table 2-6.
Input Delay Resources (IDELAY) Figure 2-12 shows an IDELAY (IDELAY_TYPE = VARIABLE, IDELAY_VALUE = 0, and DELAY_SRC = IDATAIN) timing diagram. X-Ref Target - Figure 2-12 1 2 3 C LD CE INC DATAOUT Tap 0 Tap 1 UG471_c2_10_011811 Figure 2-12: IDELAY Timing Diagram Clock Event 1 On the rising edge of C, a reset is detected (LD is High), causing the output DATAOUT to select tap 0 as the output from the 31-tap chain. Clock Event 2 A pulse on CE and INC is captured on the rising edge of C.
Chapter 2: SelectIO Logic Resources Clock Event 0 Before LD is pulsed the tap setting and therefore CNTVALUEOUT are at an unknown value. Clock Event 1 On the rising edge of C, LD is detected as High causing the output DATAOUT to have a delay defined by the CNTINVALUE, and changing the tap setting to tap 2. The CNTVALUEOUT is updated to represent the new tap value. Clock Event 2 A pulse on CE and INC are captured on the rising edge of C. This indicates an increment operation.
IDELAYCTRL In VHDL, each template has a component declaration section and an architecture section. Each part of the template should be inserted within the VHDL design file. The port map of the architecture section should include the design signal names. IDELAYCTRL IDELAYCTRL Overview If the IDELAYE2 or ODELAYE2 primitives are instantiated, the IDELAYCTRL module must also be instantiated.
Chapter 2: SelectIO Logic Resources RDY - Ready The ready (RDY) signal indicates when the IDELAY and ODELAY modules in the specific region are calibrated. The RDY signal is deasserted if REFCLK is held High or Low for one clock period or more. If RDY is deasserted Low, the IDELAYCTRL module must be reset. The implementation tools allow RDY to be unconnected/ignored. Figure 2-15 illustrates the timing relationship between RDY and RST.
OLOGIC Resources X-Ref Target - Figure 2-16 Left Edge I/O Right Edge I/O IDELAYCTRL hclk row I/O bank (50 I/O) ug471_c2_14_021914 Figure 2-16: Relative Locations of IDELAYCTRL Modules IDELAYCTRL Usage and Design Guidelines For more information on placing and locking IDELAYCTRLs, see the constraints guide. OLOGIC Resources The OLOGIC block is located next to the I/O block (IOB). OLOGIC is a dedicated synchronous block sending data out of the FPGA through the IOB.
Chapter 2: SelectIO Logic Resources X-Ref Target - Figure 2-17 T1 D1 T2 TCE CLK TQ Q D2 CE CK S/R D1 D1 D2 OCE OQ Q D2 CE CK S/R S/R ug471_c2_15_022715 Figure 2-17: OLOGIC Block Diagram This section of the documentation discusses the various features available using the OLOGIC resources. Combinatorial Output Data and 3-State Control Path The combinatorial output paths create a direct connection from the FPGA logic to the output driver or output driver control.
OLOGIC Resources OPPOSITE_EDGE Mode In OPPOSITE_EDGE mode, both the edges of the clock (CLK) are used to capture the data from the FPGA logic at twice the throughput. This structure is similar to the Virtex-6 FPGA implementation. Both outputs are presented to the data input or 3-state control input of the IOB. The timing diagram of the output DDR using the OPPOSITE_EDGE mode is shown in Figure 2-18.
Chapter 2: SelectIO Logic Resources Output DDR Primitive (ODDR) Figure 2-20 shows the ODDR primitive block diagram. Set and Reset are not supported at the same time. Table 2-10 lists the ODDR port signals. Table 2-11 describes the various attributes available and default values for the ODDR primitive.
OLOGIC Resources Table 2-12: OLOGIC Switching Characteristics Symbol Description Setup/Hold TODCK/TOCKD D1/D2 pins Setup/Hold with respect to CLK TOOCECK/TOCKOCE OCE pin Setup/Hold with respect to CLK TOSRCK/TOCKSR SR pin Setup/Hold with respect to CLK TOTCK/TOCKT T1/T2 pins Setup/Hold with respect to CLK TOTCECK/TOCKTCE TCE pin Setup/Hold with respect to CLK Clock to Out TOCKQ CLK to OQ/TQ out TRQ SR pin to OQ/TQ out Timing Characteristics Figure 2-21 illustrates the OLOGIC output regist
Chapter 2: SelectIO Logic Resources Clock Event 4 At time TOSRCK before Clock Event 4, the SR signal (configured as synchronous reset in this case) becomes valid-High, resetting the output register and reflected at the OQ output at time TRQ after Clock Event 4. Figure 2-22 illustrates the OLOGIC ODDR register timing.
OLOGIC Resources Figure 2-23 illustrates the OLOGIC 3-state register timing. X-Ref Target - Figure 2-23 1 2 3 4 5 CLK TOTCK T1 TOTCECK TCE TOSRCK SR TOCKQ TRQ TQ UG471_c2_21_011811 Figure 2-23: OLOGIC 3-State Register Timing Characteristics Clock Event 1 • At time TOTCECK before Clock Event 1, the 3-state clock enable signal becomes valid-high at the TCE input of the 3-state register, enabling the 3-state register for incoming data.
Chapter 2: SelectIO Logic Resources Figure 2-24 illustrates IOB DDR 3-state register timing. This example is shown using DDR in opposite edge mode. For other modes add the appropriate latencies as shown in Figure 2-7, page 111.
Output Delay Resources (ODELAY)—Not Available in HR Banks Output Delay Resources (ODELAY)—Not Available in HR Banks Every HP I/O block contains a programmable absolute delay primitive called ODELAYE2. The ODELAY can be connected to an OLOGICE2/OSERDESE2 block. ODELAY is a 31-tap, wraparound, delay primitive with a calibrated tap resolution. Refer to the 7 series FPGA data sheets for delay values. It can be applied to the combinatorial output path or registered output path.
Chapter 2: SelectIO Logic Resources Table 2-13: ODELAYE2 Primitive Ports (Cont’d) Port Name Direction Width Function ODATAIN Input 1 Data input for ODELAY from the OLOGICE2/OSERDESE2. LDPIPEEN Input 1 Enables the pipeline register to load data from CNTVALUEIN. DATAOUT Output 1 Delayed data from one of two data input ports (ODATAIN and CLKIN). CNTVALUEOUT Output 5 Current delay value going to FPGA logic for monitoring tap value.
Output Delay Resources (ODELAY)—Not Available in HR Banks Pipeline Register Reset - REGRST When high, this input resets the pipeline register to all zeroes. C Pin Polarity Switch - CINVCTRL The CINVCTRL pin is used for dynamically switching the polarity of C pin. This is for use in applications when glitches are not an issue. When switching the polarity, do not use ODELAY control pins for two clock cycles.
Chapter 2: SelectIO Logic Resources ODELAY Attributes Table 2-14 summarizes the ODELAY attributes. Table 2-14: ODELAY Attribute Summary Attribute Value Default Value Description ODELAY_TYPE String: FIXED, VARIABLE, VAR_LOAD, or VAR_LOAD_PIPE FIXED Sets the type of tap delay line. FIXED delay sets a static delay value. VAR_LOAD dynamically loads tap values. VARIABLE delay dynamically adjusts the delay value.
Output Delay Resources (ODELAY)—Not Available in HR Banks ODELAY_VALUE Attribute The ODELAY_VALUE attribute specifies tap delays. The possible values are any integer from 0 to 31. The default value is zero. The value of the tap delay reverts to ODELAY_VALUE when the tap delay is reset by asserting the LD signal. In VAR_LOAD or VAR_LOAD_PIPE mode, this attribute is assumed to be zero. HIGH_PERFORMANCE_MODE Attribute When TRUE, this attribute reduces the output jitter.
Chapter 2: SelectIO Logic Resources the FPGA logic. When LD is pulsed the value present at CNTVALUEIN<4:0> will be the new tap value. As a results of this functionality the ODELAY_VALUE attribute is ignored. When used in this mode, the IDELAYCTRL primitive must be instantiated. See IDELAYCTRL Usage and Design Guidelines for more details. The control pins being used in VAR_LOAD mode are described in Table 2-7.
Output Delay Resources (ODELAY)—Not Available in HR Banks Clock Event 1 On the rising edge of C, a reset is detected (LD is High), causing the output DATAOUT to select tap 0 as the output from the 31-tap chain. Clock Event 2 A pulse on CE and INC is captured on the rising edge of C. This indicates an increment operation. The output changes without glitches from tap 0 to tap 1. See Stability after an Increment/Decrement Operation.
Chapter 2: SelectIO Logic Resources Stability after an Increment/Decrement Operation Figure 2-26 shows the ODELAY line changing from tap 0 to tap 1 in response to INC and CE commands. Clearly, when the data value at tap 0 is different from the data value at tap 1, the output must change state. However, when the data values at tap 0 and tap 1 are the same (e.g., both 0 or both 1), then the transition from tap 0 to tap 1 causes no glitch or disruption on the output.
Chapter 3 Advanced SelectIO Logic Resources Introduction The I/O functionality in 7 series FPGAs is described in Chapter 1 through Chapter 3 of this user guide. • Chapter 1 covers the electrical characteristics of input receivers and output drivers, and their compliance with many industry standards. • Chapter 2 describes the register structures dedicated for sending and receiving SDR or DDR data.
Chapter 3: Advanced SelectIO Logic Resources ISERDESE2 contains dedicated circuitry (including the OCLK input pin) to handle the strobe-to-FPGA clock domain crossover entirely within the ISERDESE2 block. This allows for higher performance and a simplified implementation.
Input Serial-to-Parallel Logic Resources (ISERDESE2) ISERDESE2 Primitive (ISERDESE2) The ISERDESE2 primitive in 7 series devices (shown in Figure 3-2) is ISERDESE2. X-Ref Target - Figure 3-2 BITSLIP Q1 CE1 Q2 CE2 Q3 CLK Q4 CLKB Q5 OCLK Q6 OCLKB Q7 CLKDIVP Q8 CLKDIV SHIFTOUT1 ISERDESE2 Primitive DYNCLKSEL SHIFTOUT2 O DYNCLKDIVSEL SHIFTIN1 SHIFTIN2 RST D DDLY OFB UG471_c3_02_090810 Figure 3-2: ISERDESE2 Primitive Table 3-1 lists the available ports in the ISERDESE2 primitive.
Chapter 3: Advanced SelectIO Logic Resources Table 3-1: ISERDESE2 Port List and Definitions (Cont’d) Port Name Type Width Description CLK Input 1 High-speed clock input. Clocks serial input data stream. See High-Speed Clock Input - CLK. CLKB Input 1 Second High speed clock input only for MEMORY_QDR mode. Always connect to inverted CLK unless in MEMORY_QDR mode. See MEMORY_QDR Interface Type. CE1, CE2 Input 1 (each) RST Input 1 Active High reset. See Reset Input - RST.
Input Serial-to-Parallel Logic Resources (ISERDESE2) X-Ref Target - Figure 3-3 OSERDESE2 Data Bits ISERDESE2 H G F E D C B A Q1 H D2 Q2 G C D3 Q3 F D D4 Q4 E E D5 Q5 D F D6 Q6 C G D7 Q7 B H D8 Q8 A A D1 B Q CLKDIV_TX D CLK_TX CLK_RX CLKDIV_RX UG471_c3_03_120910 Figure 3-3: Bit Ordering on Q1–Q8 Outputs of ISERDESE2 Ports Combinatorial Output – O The combinatorial output port (O) is an unregistered output of the ISERDESE2 module.
Chapter 3: Advanced SelectIO Logic Resources X-Ref Target - Figure 3-4 ICE CE1 D Q RST AR (To ISERDESE2 Input Registers) CE1R CLKDIV CE2 D Q RST AR CE2R CLKDIV NUM_CE CLKDIV ICE 1 X CE1 2 0 CE2R 2 1 CE1R UG471_c3_04_080310 Figure 3-4: Input Clock Enable Module When NUM_CE = 1, the CE2 input is not used, and the CE1 input is an active High clock enable connected directly to the input registers in the ISERDESE2.
Input Serial-to-Parallel Logic Resources (ISERDESE2) Serial Input Data from IDELAYE2 - DDLY The serial input data port (DDLY) is the serial (high-speed) data input port of the ISERDESE2. This port works in conjunction only with the 7 series FPGA IDELAYE2 resource. See Using D and DDLY in the ISERDESE2. Serial Input Data from OSERDESE2 - OFB The serial input data port (OFB) is the serial (high-speed) data input port of the ISERDESE2.
Chapter 3: Advanced SelectIO Logic Resources ISERDESE2 Attributes Table 3-2 summarizes all the applicable ISERDESE2 attributes. A detailed description of each attribute follows the table. For more information on applying these attributes in UCF, VHDL, or Verilog code, refer to the Xilinx ISE Software Manual. Table 3-2: ISERDESE2 Attributes Attribute Name Description Default Value Value DATA_RATE Enables incoming data stream to be processed as SDR or DDR data. See DATA_RATE Attribute.
Input Serial-to-Parallel Logic Resources (ISERDESE2) Table 3-2: ISERDESE2 Attributes (Cont’d) Attribute Name Description Default Value Value SRVAL_Q2 Sets the value after reset of the second sample register. Binary: 0 or 1 1 SRVAL_Q3 Sets the value after reset of the third sample register. Binary: 0 or 1 1 SRVAL_Q4 Sets the value after reset of the fourth sample register. Binary: 0 or 1 1 IOBDELAY Sets whether an input delay applies to registered and/or non-registered outputs.
Chapter 3: Advanced SelectIO Logic Resources X-Ref Target - Figure 3-5 D Q1 FF0 ICE FF2 FF6 ICE Q2 FF1 ICE FF3 FF7 ICE CLK Q3 FF4 FF8 Q4 FF5 FF9 OCLK CLKDIV Figure 3-5: ug471_c3_05_012211 Internal Connections of ISERDESE2 When in MEMORY Mode NUM_CE Attribute The NUM_CE attribute defines the number of clock enables (CE1 and CE2) used. The possible values are 1 and 2 (default = 2).
Input Serial-to-Parallel Logic Resources (ISERDESE2) X-Ref Target - Figure 3-6 BUFIO Clock Input ISERDESE2 CLK BUFR (÷X) CLKDIV ug471_c3_06_080310 Figure 3-6: Clocking Arrangement Using BUFIO and BUFR The only valid clocking arrangements for the ISERDESE2 block using the networking interface type are: • CLK driven by BUFIO, CLKDIV driven by BUFR • CLK driven by MMCM or PLL, CLKDIV driven by CLKOUT[0:6] of same MMCM or PLL • CLK driven by BUFG, CLKDIV driven by a different BUFG When using a MMC
Chapter 3: Advanced SelectIO Logic Resources in this mode. The only valid clocking arrangements for the OVERSAMPLE interface type are: • CLK and CLKB are driven by a BUFIO. OCLK and OCLKB are driven by a BUFIO that is phase shifted by 90°. The two BUFIOs are driven from a single MMCM. • CLK and CLKB are driven by a BUFG. OCLK and OCLKB are driven by a BUFG that is phase shifted by 90°. The BUFGs are driven from a single MMCM.
Input Serial-to-Parallel Logic Resources (ISERDESE2) MEMORY_DDR3 Interface Type The MEMORY_DDR3 mode has a complex clocking structure as a result of the DDR3 memory requirements. This INTERFACE_TYPE attribute setting is only supported when using the MIG tool. ISERDESE2 Width Expansion Two ISERDESE2 modules can be used to build a serial-to-parallel converter larger than 1:8. In every I/O tile there are two ISERDESE2 modules; one master and one slave.
Chapter 3: Advanced SelectIO Logic Resources 4. The SLAVE uses the ports Q3 to Q8 as outputs. 5. DATA_WIDTH applies to both MASTER and SLAVE in Figure 3-8. ISERDESE2 Latencies When the ISERDESE2 interface type is MEMORY, the latency through the OCLK stage is one CLKDIV cycle. However, the total latency through the ISERDESE2 depends on the phase relationship between the CLK and the OCLK clock inputs. When the ISERDESE2 interface type is NETWORKING, the latency is two CLKDIV cycles.
Input Serial-to-Parallel Logic Resources (ISERDESE2) Using D and DDLY in the ISERDESE2 The D and DDLY pins are dedicated inputs to the ISERDESE2. The D input is a direct connection to the IOB. The DDLY pin is a direct connection to the IDELAYE2. This allows the user to either have a delayed or non-delayed version of the input to the registered (Q1-Q8) or combinatorial path (O) output. The attribute IOBDELAY determines the input applied to the ISERDESE2.
Chapter 3: Advanced SelectIO Logic Resources names do not change when a different bus input width, including when two ISERDESE2 are cascaded together to form 10 or 14 bits. In DDR mode, the data input (D) switches at every CLK edge (rising and falling).
Input Serial-to-Parallel Logic Resources (ISERDESE2) a shift right by one and shift left by three. In this example, on the eighth Bitslip operation, the output pattern reverts to the initial pattern. This assumes that serial data is an eight bit repeating pattern. Although the repeating pattern seems to show that bitslip is a barrel shifting operation, this is not the case. A bitslip operation adds one bit to the input data stream and loses the nth bit in the input data stream.
Chapter 3: Advanced SelectIO Logic Resources Bitslip Timing Model and Parameters This section discusses the timing models associated with the Bitslip controller in a 1:4 DDR configuration. Data (D) is a repeating, 4-bit training pattern ABCD. ABCD could appear at the parallel outputs Q1–Q4 of the ISERDESE2 in four possible ways: ABCD, BCDA, CDAB, and DABC.
Output Parallel-to-Serial Logic Resources (OSERDESE2) Output Parallel-to-Serial Logic Resources (OSERDESE2) The OSERDESE2 in 7 series devices is a dedicated parallel-to-serial converter with specific clocking and logic resources designed to facilitate the implementation of high-speed source-synchronous interfaces. Every OSERDESE2 module includes a dedicated serializer for data and 3-state control. Both data and 3-state serializers can be configured in SDR and DDR mode.
Chapter 3: Advanced SelectIO Logic Resources 3-State Parallel-to-Serial Conversion In addition to parallel-to-serial conversion of data, an OSERDESE2 module also contains a parallel-to-serial converter for 3-state control of the IOB. Unlike data conversion, the 3-state converter can only serialize up to four bits of parallel 3-state signals. The 3-state converter cannot be cascaded. OSERDESE2 Primitive The OSERDESE2 primitive is shown in Figure 3-14.
Output Parallel-to-Serial Logic Resources (OSERDESE2) OSERDESE2 Ports Table 3-6 lists the available ports in the OSERDESE2 primitive. Table 3-6: OSERDESE2 Port List and Definitions Port Name Type Width Description OQ Output 1 Data path output to IOB only. See Data Path Output - OQ. OFB Output 1 Data path output feedback to ISERDESE2 or connection to ODELAYE2. See Output Feedback. TQ Output 1 3-state control output to IOB. See 3-state Control Output - TQ.
Chapter 3: Advanced SelectIO Logic Resources 3-state Control Output - TQ This port is the 3-state control output of the OSERDESE2 module. When used, this port connects the output of the 3-state parallel-to-serial converter to the control/3-state input of the IOB. 3-state Control Output - TFB This port is the 3-state control output of the OSERDESE2 module sent to fabric if required by the user. It indicates that the OSERDESE2 is 3-stated.
Output Parallel-to-Serial Logic Resources (OSERDESE2) OSERDESE2 Attributes The Table 3-7 lists and describes the various attributes that are available for the OSERDESE2 primitive. The table includes the default values. Table 3-7: OSERDESE2 Attribute Summary Attribute Description Value Default Value DATA_RATE_OQ Defines whether data (OQ) changes at every clock edge or every positive clock edge with respect to CLK.
Chapter 3: Advanced SelectIO Logic Resources DATA_WIDTH Attribute The DATA_WIDTH attribute defines the parallel data input width of the parallel-to-serial converter. The possible values for this attribute depend on the DATA_RATE_OQ attribute. When DATA_RATE_OQ is set to SDR, the possible values for the DATA_WIDTH attribute are 2, 3, 4, 5, 6, 7, and 8. When DATA_RATE_OQ is set to DDR, the possible values for the DATA_WIDTH attribute are 4, 6, 8, 10, and 14.
Output Parallel-to-Serial Logic Resources (OSERDESE2) OSERDESE2 Width Expansion The OSERDESE2 modules be used to build a parallel-to-serial converter larger than 8:1. In every I/O tile there are two OSERDESE2 modules; one master and one slave. By connecting the SHIFTIN ports of the master OSERDESE2 to the SHIFTOUT ports of the slave OSERDESE2, the parallel-to-serial converter can be expanded to up to 10:1 and 14:1 (DDR mode only).
Chapter 3: Advanced SelectIO Logic Resources Table 3-9 lists the data width availability for SDR and DDR mode. Table 3-9: OSERDESE2 SDR/DDR Data Width Availability SDR Data Widths 2, 3, 4, 5, 6, 7, 8 DDR Data Widths 4, 6, 8, 10, 14 Guidelines for Expanding the Parallel-to-Serial Converter Bit Width 1. Both the OSERDESE2 modules must be adjacent master and slave pairs. 2. Set the SERDES_MODE attribute for the master OSERDESE2 to MASTER and the slave OSERDESE2 to SLAVE. See SERDES_MODE Attribute.
Output Parallel-to-Serial Logic Resources (OSERDESE2) Table 3-11: OSERDESE2 Latencies DATA_RATE DATA_WIDTH SDR DDR Latency 2:1 1 CLK cycle 3:1 2 CLK cycles 4:1 3 CLK cycles 5:1 4 CLK cycles 6:1 5 CLK cycles 7:1 6 CLK cycles 8:1 7 CLK cycles 4:1 2 CLK cycles 6:1 3 CLK cycles 8:1 4 CLK cycles 10:1 5 CLK cycles 14:1 7 CLK cycles OSERDESE2 Timing Model and Parameters This section discusses all timing models associated with the OSERDESE2 primitive.
Chapter 3: Advanced SelectIO Logic Resources Timing Characteristics of 2:1 SDR Serialization In Figure 3-16, the timing of a 2:1 SDR data serialization is illustrated.
Output Parallel-to-Serial Logic Resources (OSERDESE2) Timing Characteristics of 8:1 DDR Serialization Figure 3-17 illustrates the timing of an 8:1 DDR data serialization. All eight of the bits are connected to D1–D6 of the master OSERDESE2 in contrast to previous generations where cascading was required. X-Ref Target - Figure 3-17 Clock Event 2 Clock Event 1 Clock Event 3 Master.D1 A I Master.D2 B J Master.D3 C K Master.D4 D L Master.D5 E M Master.D6 F N Master.D7 G O Master.
Chapter 3: Advanced SelectIO Logic Resources Clock Event 4 Between Clock Events 3 and 4, the entire word ABCDEFGH is transmitted serially on OQ, a total of eight bits transmitted in one CLKDIV cycle. The data bit I appears at OQ four CLK cycles after IJKLMNOP is sampled into the OSERDESE2. This latency is consistent with the Table 3-11 listing of a 8:1 DDR mode OSERDESE2 latency of four CLK cycles.
IO_FIFO Overview Clock Event 2 The data bit E appears at OQ one CLK cycle after EFGH is sampled into the OSERDESE2. This latency is consistent with the Table 3-11 listing of a 4:1 DDR mode OSERDESE2 latency of one CLK cycle. The 3-state bit 0 at T1 during Clock Event 1 appears at TQ one CLK cycle after 0010 is sampled into the OSERDESE2 3-state block. This latency is consistent with the Table 3-11 listing of a 4:1 DDR mode OSERDESE2 latency of one CLK cycle.
Chapter 3: Advanced SelectIO Logic Resources The IO_FIFOs have an input register, a 7-entry deep FIFO core, and an output register (see Figure 3-19). The input and output registers are an integral part of the IO_FIFO and provide the eighth storage location for the full IO_FIFO. The registers, FIFO core, and control signals are treated as a single atomic unit.
IO_FIFO Overview Table 3-13: IN_FIFO Input to Output Data Mapping in 4 x 4 Mode (Cont’d) Mapping Not Used D5[3:0] → Q5[3:0] D6[3:0] → Q6[3:0] D7[3:0] → Q7[3:0] Q7[7:4] D8[3:0] → Q8[3:0] Q8[7:4] D9[3:0] → Q9[3:0] Q9[7:4] D10[3:0] is D5[7:4] → Q5[7:4] D11[3:0] is D6[7:4] → Q6[7:4] • 4 x 8 mode – This mode configures the FIFO to have 10 4-bit wide data inputs (D) and 10 8-bit wide data outputs (Q). In 4 x 8 mode, the 4-bit input data is demultiplexed to form the 8-bit output data width.
Chapter 3: Advanced SelectIO Logic Resources X-Ref Target - Figure 3-20 D0[3:0] Q0[7:0] D1[3:0] Q1[7:0] D2[3:0] Q2[7:0] D3[3:0] Q3[7:0] D4[3:0] Q4[7:0] D5[7:0] (1) (1) Q5[7:0] D6[7:0] (1) (1) Q6[7:0] D7[3:0] Q7[7:0] D8[3:0] Q8[7:0] D9[3:0] Q9[7:0] RDEN EMPTY WREN FULL RDCLK ALMOSTEMPTY WRCLK ALMOSTFULL RESET Notes: 1. Extra input ports D10 (D5[7:4]) and D11 (D6[7:4]) and output ports Q10 (Q5[7:4]) and Q11 (Q5[7:4]) in 4 x 4 mode.
IO_FIFO Overview Table 3-15: IN_FIFO Ports (Cont’d) Port Name Input/output Description Q5[7:4], Q6[7:4] O Supplemental data out ports Q10 and Q11. Used only in 4x4 mode. Data on these ports is sourced from corresponding input ports D5[7:4] and D6[7:4]. EMPTY O Empty flag. Synchronized to RDCLK. O Full flag. Synchronized to WRCLK. ALMOSTEMPTY O Programmable level empty flag. Synchronized to RDCLK. ALMOSTFULL(1) O Programmable level full flag. Synchronized to WRCLK. FULL (1) Notes: 1.
Chapter 3: Advanced SelectIO Logic Resources used when the output clock frequency is twice the input clock frequency and thus output data is half the width of the input data. Table 3-17 shows the 8 x 4 mode mapping in detail.
IO_FIFO Overview X-Ref Target - Figure 3-21 D0[7:0] Q0[3:0] D1[7:0] Q1[3:0] D2[7:0] Q2[3:0] D3[7:0] Q3[3:0] D4[7:0] Q4[3:0] D5[7:0] (1) (1) Q5[7:0] D6[7:0] (1) (1) Q6[7:0] D7[7:0] Q7[3:0] D8[7:0] Q8[3:0] D9[7:0] Q9[3:0] RDEN EMPTY WREN FULL RDCLK ALMOSTEMPTY WRCLK ALMOSTFULL RESET Notes: 1. Extra input ports D10 (D5[7:4]) and D11 (D6[7:4]) and output ports Q10 (Q5[7:4]) and Q11 (Q5[7:4]) in 4 x 4 mode.
Chapter 3: Advanced SelectIO Logic Resources Table 3-18: OUT_FIFO Ports (Cont’d) Port Name Input/output Description Q5[7:4], Q6[7:4] O Supplemental data out ports Q10 and Q11. Used only in 4 x 4 mode. Data on these ports is sourced from the corresponding input ports D5[7:4] and D6[7:4]. EMPTY O Empty flag. Synchronized to RDCLK. O Full flag. Synchronized to WRCLK. ALMOSTEMPTY O Programmable level empty flag. Synchronized to RDCLK. ALMOSTFULL(1) O Programmable level full flag.
IO_FIFO Overview Table 3-19: . IO_FIFO Attributes Attribute Value Default Value ARRAY_MODE (IN_FIFO) String: ARRAY_MODE_4_X_8 ARRAY_MODE_4_X_4 ARRAY_MODE_4_X_8 Defines 4 input bits and 4 or 8 output bits per port. ARRAY_MODE (OUT_FIFO) String: ARRAY_MODE_8_X_4 ARRAY_MODE_4_X_4 ARRAY_MODE_8_X_4 Defines 4 or 8 input bits, and 4 output bits per port. ALMOST_EMPTY_VALUE Integer: 1 or 2 1 See ALMOST EMPTY and ALMOST FULL Flags, page 178.
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Appendix A Termination Options for SSO Noise Analysis The PlanAhead™ software has the ability to perform simultaneous switching noise (SSN) analysis for each design, taking into account the actual I/O standards and options assigned to the I/O pins in the target device and package. For details on how to use this feature and perform the SSN analysis, see the “Using Noise Analysis Predictors” section of UG632: PlanAhead User Guide.
Appendix A: Termination Options for SSO Noise Analysis Table A-1: Default Terminations for SSN Noise Analysis by I/O Standard (Cont’d) IO Standard(1) LVCMOS (all voltages) Default Termination Far VTT 50Ω LVTTL (12 mA, 16 mA, and 24 mA drive) 182 MOBILE_DDR None SSTL12 Far VTT 50Ω SSTL12_DCI Far VTT 50Ω SSTL12_T_DCI Far VTT 50Ω SSTL135 Far VTT 50Ω SSTL135_DCI Far VTT 50Ω SSTL135_R Far VTT 50Ω SSTL135_T_DCI Far VTT 50Ω SSTL15 Far VTT 50Ω SSTL15_DCI Far VTT 50Ω SSTL15_R Far VTT 50Ω
Table A-1: Default Terminations for SSN Noise Analysis by I/O Standard (Cont’d) IO Standard(1) TMDS_33 Default Termination Far 3.3V 50Ω Notes: 1. All differential versions of the HSTL, SSTL, HSUL, and MOBILE_DDR standards (e.g., DIFF_SSTL135) have the same termination as the single-ended versions. Figure A-1 illustrates each of these terminations. 7 Series FPGAs SelectIO Resources User Guide UG471 (v1.5) May 15, 2015 www.xilinx.
Appendix A: Termination Options for SSO Noise Analysis X-Ref Target - Figure A-1 50Near-end Parallel Termination to VTT 50Far-end Parallel Termination to VTT NP_VTT_50_FP_VTT_50 Unterminated Z=50 VTT = VCCO/2 VTT = VCCO/2 50 50 50Far-end Parallel Termination to VCCO FP_VCCO_50 Z=50 VCCO 100Far-end Differential Termination FD_100 50 Z=50 ZDIFF=100 100 1KFar-end Parallel Termination to VCCO FP_VCCO_1000 VCCO 165Near Series, 140Near Differential, 100Far Differential NS_1
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Appendix A: Termination Options for SSO Noise Analysis 186 Send Feedback www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide UG471 (v1.
