Specifications

performance and
scalability
The HP Server rp8400 brings leading-edge performance and scalability to the midrange server
market. At first release, the rp8400 already has an industry-leading OLTP performance
benchmark. When density is added to the equation, the compact rp8400 offers performance
density at least twice that of the competition. For example, two rp8400 servers fit into a single
HP cabinet, with room to spare for 2.4 TB of storage. Competitive systems, on the other hand,
require at least two cabinets, or even four, to equal the rp8400 performance.
Designed to scale well into the future, the rp8400 has plenty of headroom to support a long list
of future upgrades. Several generations of processors, including Intel Itanium Processor Family
and dual-die processors, will be supported. In addition, more memory, I/O, and manageability
features will be added at each release, further improving performance and scalability.
This section summarizes the main performance and scalability characteristics of the rp8400.
important speeds and feeds
Crossbar bandwidth (peak)
16 GB/s
Cell-controller-to-I/O-subsystem bandwidth (peak)
4 GB/s
I/O slot bandwidth (peak)
8.5 GB/s
Memory bus bandwidth (peak)
16 GB/s
scalability
Hot-plug cell boards 1–4
CPUs 2–16
Memory 1–64 GB
Hot-plug PCI I/O slots 16 slots (64-bit x 66 MHz)
Partitions 1 or 2
Hot-plug internal disks 0–4 (18- or 36-GB disks)
Hot-plug removable media 0–2 (DVD or DAT)
performance benchmarks
The HP server rp8400 offers leadership performance in the OLTP, business intelligence, and
technical markets. More information will be available as benchmarks become certified.
performance considerations
In order to achieve top performance with the rp8400, a few rules apply:
and configuration rules
configuration applies to details
A cell should be configured
with a multiple of eight DIMMs.
All cells in a partition should
have the same amount of
memory (symmetric memory
loading).
Cell (memory) Eight DIMMs are required in order to
populate both memory buses. There may
be additional interleaving and/or
bandwidth benefits to populate more rows.
Populating only one memory bus (four
DIMMs on a cell) delivers half the
available bandwidth.
Cell (memory) Asymmetrically distributed memory affects
the interleaving of cache lines across the
cells. Asymmetrically distributed memory
can create memory regions that are non-
optimally interleaved. Applications whose
memory pages land in memory interleaved
across just one cell can see up to four times
less bandwidth than applications whose
pages are interleaved across all cells.
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