Specifications

crossbar chips
Two crossbar chips are part of the rp8400 system chipset. (They are also a subset of the chipset
used in the HP Superdome.) Each chip implements a high-performance 8-port non-blocking
crossbar and the 500-MHz crossbar link protocol. Together the two crossbar chips provide 16
high-performance ports for cell-to-cell communication, with 16 GB/s of aggregate bandwidth. All
ports are functionally and electrically identical. Some of the features of the crossbar chip that
contribute to performance include the following:
• support for scaling up to a 256-way Coherent Shared Memory system
• 250-MHz speed of operation
• 500-MT/s (megatransfers/second) link speed
• support for 2 interleaved channels on link protocol
• support for double-length data packets for IPF mode
• performance counters to enable software tuning
memory latency
There are two types of memory latencies within the rp8400 system:
memory latency within the cell—This latency refers to the case where an
application runs on a partition that consists of a single cell.
memory latency between cells—This type of latency is present when the partition
consists of two cells. In this case half of the addresses are to the memory on the
requesting processor’s cell, and the other half of the addresses are to the memory
of the other cell.
Memory latency in the rp8400 depends on the number of CPUs and the location of their
corresponding cell boards. Assuming that there is equally distributed access to all memory
controller, and that cell boards are installed to minimize latency, the average memory latency
(load-to-use) is shown here:
number of CPUs average memory latency
4-CPU 260ns
8-CPU 320ns
16-CPU 350ns
The idle memory latency—that is, the latency when the system is idle—is shown in this table:
number of CPUs average idle memory latency
4-CPU 200ns
8-CPU 250ns
16-CPU 295ns
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