System Debug Reference Manual (32650-90888)

Chapter 4 143
System Debug Command Specifications :-Exit
ENV
The names may be abbreviated to 1 character.
The default is based on the current mode (NM or CM). Refer to the SET
command for an alternate method of setting this variable.
IOR U32 (nmreg) r dM
NM interrupt offset register. (Alias for CR21)
IPSW U32 (nmreg) r dM
NM interrupt processor status word (alias for CR22 and PSW). Debug may
set or alter the "R" bit while single stepping, as well as the "T" bit if the
TRAP BRANCH ARM command has been issued.
This register has the following format:
1 1 1 1 1 1 1 2 2 2 2 3 3
0 7 8 9 0 1 2 3 4 5 6 4 7 8 9 0 1
-----------------------------------------------------------------
|J| |T|H|L|N|X|B|C|V|M| C/B | |R|Q|P|D|I|
-----------------------------------------------------------------
J Joint instruction and data TLB misses/page faults pending
T Taken branch trap enabled
H Higher-privilege transfer trap enable
L Lower-privilege transfer trap enable
N Instruction whose address is at front of PC queue is
nullified
X Data memory break disable
B Taken branch in previous cycle
C Code address translation enable
V Divide step correction
M High-priority machine check disable
C/B Carry/borrow bits
R Recovery counter enable
Q Interruption state collection enable
P Protection ID validation enable
D Data address translation enable
I External, power failure, & low-priority machine check
interruption enable
System Debug displays this register in two formats:
IPSW=$6ff0b=jthlnxbCVmrQpDI
The first value is a full 32-bit integer representation of the register. The
second format shows the value of the special named bits. An uppercase