System Debug Reference Manual (32650-90888)

126 Chapter4
System Debug Command Specifications :-Exit
DR
The following registers are known as the Control Registers. They contain system state
information.
SR4 none dM Process local code space (tracks PC
space)
SR5 none dM Process local data space
SR6 none dM Operating system data space 1
SR7 none dM Operating system data space 2
Table 4-4. Control Registers
Name Alias Access Description
CR0 RCTR dM Recovery counter
CR8 PID1 dM Protection ID 1 (16 bits)
CR9 PID2 dM Protection ID 2 (16 bits)
CR10 CCR dM Coprocessor configuration (8 bits)
CR11 SAR dm Shift amount register (5 bits)
CR12 PID3 dM Protection ID 3 (16 bits)
CR13 PID4 dM Protection ID 4 (16 bits)
CR14 IVA dM Interrupt vector address
CR15 EIEM dM External interrupt enable mask
CR16 ITMR dM Interval timer
CR17 PCSF dM PC space queue front
none PCSB dM PC space queue back
CR18 PCOF dM PC offset queue front
none PCSB dM PC offset queue back
none PCQF dM PC queue (PCOF.PCSF) front
none PCQB dM PC queue (PCOB.PCSB) back
none PC dM PCQF with priv bits set to zero.
none PRIV dM Low two order bits (30,31) of PCOF.
CR19 IIR dM Interrupt instruction register
CR20 ISR dM Interrupt space register
CR21 IOR dM Interrupt offset register
Table 4-3. Space Registers
Name Alias Access Description