Technical data

Troubleshooting
Dealing with HPMC (Uncorrectable Error)
4-23
HPMC Caused by a Multi-Bit Memory Parity Error
An HPMC interruption is forced when a multi-bit memory parity error is detected during a
“DMA read” operation or fetching an I/D cache line (32 bytes).
Table 4-6 shows an example of the HPMC error information retrieved from Stable Storage
by the PIM command from the Interactive Testing Debug Environment.
Interpreting the Table
The values in the Bus Check and System Responder Address words indicate that a multi-
bit memory parity error was detected by logic in the memory module. Ignore the value in
the System Controller Status word.
The System Responder contains the hexadecimal address of the faulty memory location.
Read the following section, Determining the Faulty Memory Card, to determine which
memory card contains the faulty memory location.
Table 4-6 Multi-Bit Memory Parity Error
Word Value
Check Type 0x20000000
CPU State 0x9e000004
Cache Check 0x00000000
TLB check 0x00000000
Bus Check 0x00210004
Assists Check 0x00000000
Assists State 0x00000000
System Responder Address 0xnnnnnnnn
System Requester Address 0x00000000
System Controller Status 0x00000nnn